Polycrystalline Silicon Nanowire Transistors on Bulk Substrates
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Solution Overview
Problem
The challenge is to develop a semiconductor device with improved performance and reduced costs, as nanowire transistors on bulk silicon substrates face lower mobility and higher variability due to polycrystalline silicon's poorer performance compared to monocrystalline silicon, and the use of SOI substrates is costly.
Innovation Solution
A method for manufacturing polycrystalline silicon nanowire transistors involves forming nanowire regions with oblique ion implantation for amorphization and subsequent crystal growth using seed crystals from source and drain regions, increasing crystal grain size and improving mobility, while using a bulk silicon substrate to reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polycrystalline silicon nanowires are used on bulk silicon substrate, then manufacturing cost is reduced, but mobility and device performance deteriorate due to crystal grain boundaries
Solution Approach 1:
The patent applies local quality by making the nanowire channel regions monocrystalline while keeping other regions polycrystalline. This is achieved through selective epitaxial growth that grows single crystals only in the nanowire regions where high mobility is needed, while the bulk substrate remains polycrystalline. This resolves the contradiction by providing monocrystalline quality exactly where required for device performance while maintaining the cost advantage of polycrystalline manufacturing elsewhere.
Solution Approach 2:
The patent changes the crystalline structure parameter from polycrystalline to monocrystalline specifically in the nanowire channel regions. This is accomplished through controlled epitaxial growth conditions that promote single crystal formation in the nanowires while maintaining polycrystalline structure in the bulk. This parameter change directly addresses the mobility issue caused by crystal grain boundaries while preserving the cost benefits of bulk substrate manufacturing.
2Reliability
If SOI substrate is used, then leak current is restrained and manufacturing is simplified, but manufacturing cost increases
Solution Approach 1:
The patent extracts the essential function of the SOI buried oxide layer (providing electrical isolation and restraining leak current) and implements it through a different structure. Instead of using a buried oxide layer on an expensive SOI substrate, the patent uses a monocrystalline nanowire channel grown on a bulk substrate with appropriate isolation structures. This extracts the leak current control function while avoiding the high cost of SOI substrates.
Solution Approach 2:
The patent replaces the expensive SOI substrate with a cheaper bulk silicon substrate. The bulk substrate serves the same electrical isolation function through proper device design and doping structures, eliminating the need for the costly SOI structure while maintaining leak current control. This substitution of a cheaper material achieves the same functional outcome.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the ON-state current, reduces OFF-state current, and decreases variations in device characteristics, achieving performance comparable to SOI-based transistors at a lower cost by increasing crystal grain size and improving ion implantation techniques.
Implementation Method 1
performing first ion implantation to implant ions into the side faces of the first region of the first semiconductor layer
Implementation Method 2
performing a first heat treatment, after the first ion implantation is performed
Data Source
AI summary
A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.