Group III-N Nanowire Transistors Gate-All-Around Integration
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Solution Overview
Problem
Conventional mobile computing platforms face limitations in scalability and integration due to the use of multiple transistor technologies, which hinder advancements in functionality, integration, cost, and form factor, primarily because of the lack of scalable transistor technologies that can achieve high gain cutoff frequency and breakdown voltage while managing high voltage and power efficiently.
Innovation Solution
The development of group III-nitride semiconductor nanowires with a 'gate-all-around' design enables the fabrication of high voltage, high bandwidth field effect transistors, allowing for ultra-scaling into the sub-100 nm regime, combining high frequency operation with high breakdown voltage, suitable for broadband wireless data transmission and high speed switching applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional transistor technologies are used in mobile computing platforms, then high voltage and power can be managed, but scalability and integration are limited due to the need for multiple transistor technologies
Solution Approach 1:
The patent applies universality by developing a single transistor technology (group III-nitride HEMT) that can perform multiple functions previously requiring different transistor types. The device can operate in both high voltage/power modes and low voltage modes, replacing the need for separate high voltage transistors, power amplifiers, and logic transistors with one unified device architecture.
Solution Approach 2:
The patent merges multiple transistor technologies into a single group III-nitride HEMT platform. By combining the functionalities of high voltage transistors, power amplifiers, and logic transistors into one device type, the patent reduces device complexity and enables better integration while maintaining high voltage, high frequency, and low voltage operational capabilities.
2Speed
If group III-nitride transistors are scaled to feature sizes less than 100 nm, then high gain cutoff frequency can be achieved, but short channel effects become difficult to control
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar gate control to three-dimensional gate-all-around control of the nanowire channel. This vertical wrapping of the gate electrode around the nanowire provides electrostatic control from all directions, effectively suppressing short channel effects while enabling ultra-scaled feature sizes and high gain cutoff frequencies.
Solution Approach 2:
The patent segments the gate structure into multiple regions that wrap around the nanowire channel, with different gate sections independently controllable. This segmentation allows precise electrostatic control of the channel from all angular directions, maintaining reliability at sub-100 nm scales while achieving high frequency operation.
3Power
If multiple transistor technologies are used for high voltage, high power, and high frequency operations, then sufficient power amplification can be achieved, but scalability is limited
Solution Approach 1:
The patent creates a universal transistor platform that delivers high power amplification capability across all operating modes. The group III-nitride HEMT with gate-all-around control can provide sufficient power amplification at RF frequencies while also handling high voltage switching and low voltage logic operations, enabling scalable integration without requiring multiple specialized transistor technologies.
Data Source
AI summary
A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.