Nanowire Transistors With Graded Tip Regions
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Solution Overview
Problem
High-voltage transistors suffer from high leakage currents, and existing fin-based transistors do not provide the same benefits as nanowire devices in terms of improved short-channel effects, necessitating the development of nanowire or nanoribbon devices with graded tip regions to reduce leakage.
Innovation Solution
The implementation of nanowire or nanoribbon transistors with graded tip regions, where the tip regions have a higher doping concentration than the middle portion of the nanowire, extending into the channel region and wrapped with a gate dielectric and electrode, allowing for improved control over channel lengths and voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If nanowire devices use thicker gate oxides for high voltage applications, then voltage handling capability is improved, but the space between nanowires is reduced to the point that little or no gate metal can be disposed between the nanowires
Solution Approach 1:
The patent transitions from planar gate metal configuration to a three-dimensional wrapped gate structure that surrounds each nanowire completely. This dimensional change allows the gate to accommodate thicker oxides while maintaining adequate spacing, as the gate wraps around the nanowire perimeter rather than requiring lateral space between adjacent nanowires.
Solution Approach 2:
The gate structure is nested around each individual nanowire, with the gate dielectric and gate metal forming concentric layers that wrap around the nanowire. This nested configuration allows thick gate oxides to be implemented without reducing the spacing between adjacent nanowires, as each gate is self-contained around its respective nanowire.
2Power
If high voltage transistors are implemented, then power application capability is improved, but leakage current increases
Solution Approach 1:
The patent applies different doping concentrations to different regions of the nanowire - specifically, higher doping at the tip regions and lower doping in the channel region. This local quality variation allows the transistor to handle high voltages while suppressing leakage currents through optimized carrier distribution in critical regions.
Solution Approach 2:
The patent changes the doping concentration parameter along the nanowire length, creating graded tip regions with higher doping than the channel region. This parameter variation enables high voltage operation by strengthening the electric field control at critical interfaces while maintaining low leakage through reduced doping in the channel.
3Productivity
If feature sizes are shrunk to achieve greater circuit density, then device density is improved, but short-channel effects and parasitic capacitance increase
Solution Approach 1:
The patent employs a three-dimensional wrapped gate structure that surrounds the nanowire completely, providing gate control from all directions. This dimensional approach enhances electrostatic control and suppresses short-channel effects even as feature sizes are reduced, allowing continued scaling while maintaining device performance.
Solution Approach 2:
The patent uses a composite structure consisting of the nanowire channel, gate dielectric, and gate metal in a wrapped configuration. This composite architecture provides superior electrostatic control compared to planar structures, enabling reduced feature sizes while mitigating short-channel effects through the combined geometric and material properties.
Data Source
Figure 1A
Figure 1B
Figure 2A~2B
AI summary
Embodiments disclosed herein include nanoribbon and nanowire semiconductor devices. In an embodiment, the semiconductor device comprises a nanowire disposed above a substrate. In an embodiment, the nanowire has a first dopant concentration, and the nanowire comprises a pair of tip regions on opposite ends of the nanowire. In an embodiment, the tip regions comprise a second dopant concentration that is greater than the first dopant concentration. In an embodiment, the semiconductor device further comprises a gate structure over the nanowire. In an embodiment, the gate structure is wrapped around the nanowire, and the gate structure defines a channel region of the device. In an embodiment, a pair of source/drain regions are on opposite sides of the gate structure, and both source/drain regions contact the nanowire.