Nanowire Transistors With Multiple Threshold Voltages
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Solution Overview
Problem
As microelectronic device dimensions scale past the 15 nm node, achieving high mobility and short channel control in nanowire transistors becomes challenging, and manufacturing systems with multiple discrete devices for different functions face issues with complexity, footprint, and cost.
Innovation Solution
The method involves forming nanowire devices with multiple threshold voltages on a single substrate by using a self-aligned technique to create gate cavities with specific geometries, allowing for the tuning of threshold voltages through gate stack configuration differentiation, enabling the fabrication of devices with disparate characteristics on a single chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple discrete devices are used for different functions, then device characteristics can be optimized for specific functions, but system complexity and manufacturing complexity increase
Solution Approach 1:
The patent combines multiple nanowire devices with different threshold voltage characteristics onto a single substrate by forming different gate stack configurations in different regions. This merging approach allows disparate device characteristics to coexist on one chip, reducing the need for multiple separate devices while maintaining optimized performance for different functions.
Solution Approach 2:
The patent implements local quality by creating region-specific gate stack configurations on the substrate. Different regions have different gate electrode thicknesses, materials, or structures tailored to achieve specific threshold voltages for different device functions, allowing each region to be optimized for its intended purpose while maintaining overall system integration.
2Adaptability or versatility
If multiple discrete devices are used for different functions, then device characteristics can be optimized for specific functions, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple nanowire devices with different threshold voltage characteristics onto a single substrate by forming different gate stack configurations in different regions. This merging approach allows disparate device characteristics to coexist on one chip, reducing the need for multiple separate devices while maintaining optimized performance for different functions.
3Productivity
If nanowire devices are scaled to smaller dimensions, then device density increases, but achieving high mobility and short channel control becomes challenging
Solution Approach 1:
The patent employs dynamic gate stack configurations where gate electrode thickness, material composition, and structure can be varied across different regions of the substrate. This dynamic approach allows optimization of threshold voltage and channel control for each specific device region, enabling effective short channel control even as devices are scaled to smaller dimensions and higher densities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the manufacturing of nanowire devices with varied threshold voltages on a single substrate, enhancing design flexibility and reducing manufacturing complexity and costs while maintaining high mobility and short channel control.
Implementation Method 1
depositing a first sacrificial layer on a semiconductor substrate, where the first sacrificial layer has a first thickness in a first region of the substrate and a second thickness greater than the first thickness in a second region of the substrate
Implementation Method 2
selectively etching the first and second sacrificial layers to form first cavities within the first region and second cavities within the second region
Implementation Method 3
A work function metal layer is deposited on the dielectric layer within the first cavities and on the dielectric layer within the second cavities, such that the work function metal layer substantially fills the first and second cavities
Data Source
AI summary
Multi-threshold voltage (Vt) nanowire devices are fabricated using a self-aligned methodology where gate cavities having a predetermined geometry are formed proximate to channel regions of respective devices. The gate cavities are then backfilled with a gate conductor. By locally defining the cavity geometry, the thickness of the gate conductor is constrained and hence the threshold voltage for each device can be defined using a single deposition process for the gate conductor layer. The self-aligned nature of the method obviates the need to control gate conductor layer thicknesses using deposition and/or etch processes.