Nanowire Tunnel FET Source Doping Uniformity
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Solution Overview
Problem
Current nanowire tunnel field effect transistors face challenges in optimizing the structure and doping of source and drain regions, which affect the device's performance and efficiency.
Innovation Solution
The development of a nanowire tunnel field effect transistor with a silicon channel region surrounded by a gate structure, featuring a doped epi-silicon source region epitaxially grown in a cavity and an n-type doped silicon drain region, optimized through specific etching and epitaxial growth processes to enhance doping uniformity and junction abruptness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping methods are used in nanowire tunnel FETs, then the doping process is simpler, but the doping uniformity and junction abruptness are insufficient
Solution Approach 1:
The nanowire structure is segmented into distinct regions: a silicon channel portion, a cavity region, and an epi-silicon source region. This segmentation allows independent optimization of each region, enabling precise control over doping uniformity in the source region and abruptness at the junction between the epi-silicon source and silicon channel, while maintaining a manageable overall device structure.
Solution Approach 2:
The cavity is formed beforehand by etching the silicon substrate before epitaxial growth of the source region. This preliminary action creates a defined space that confines the dopant distribution during subsequent ion implantation, ensuring uniform doping within the source region and sharp junction formation at the cavity boundaries without requiring complex in-situ doping control.
2Reliability
If the source and drain regions are optimized for better performance, then the transistor efficiency improves, but the device structure and doping processes become more complex
Solution Approach 1:
Different regions of the nanowire are assigned different materials and doping characteristics tailored to their specific functions: the silicon channel portion provides carrier transport, while the epi-silicon source region in the cavity provides uniform doping and abrupt junctions. This local optimization enhances transistor performance without requiring complex structures throughout the entire device.
Solution Approach 2:
The epi-silicon source region is nested within the cavity formed in the silicon substrate, creating a hierarchical structure where the source region is contained within a defined space. This nesting approach allows for optimized source region properties while maintaining a relatively simple overall device architecture, avoiding the need for complex three-dimensional structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the uniformity of doping in the source region and creates an abrupt junction, enhancing the transistor's performance and efficiency by controlling ion implantation and epitaxial growth processes.
Implementation Method 1
nanowire tunnel field effect transistor
Implementation Method 2
field effect transistor
Implementation Method 3
controlling ion implantation processes
Implementation Method 4
controlling ion implantation and epitaxial growth processes
Data Source
AI summary
A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.