Nanowire Formation on 2D Insulating Layer via Evaporation
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Solution Overview
Problem
Current silicon-based metal oxide semiconductor field effect transistors (MOSFETs face manufacturing and property limitations, necessitating the development of next-generation materials and devices that can overcome these constraints.
Innovation Solution
A method for manufacturing nanowires using a catalyst metal layer with materials like copper, nickel, iron, cobalt, platinum, and ruthenium, where the nanowires are formed on a crystalline insulating layer through an evaporation process at specific temperature and time conditions, enabling the creation of semiconductor devices with improved performance and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional silicon-based MOSFET manufacturing methods are used, then existing process compatibility is maintained, but manufacturing precision and device performance are limited by current process capabilities
Solution Approach 1:
The patent changes the substrate temperature parameter to a specific range (340-420°C) during evaporation deposition to enable precise nanowire formation with controlled diameter (5-50 nm) and length (1-10 μm), achieving high manufacturing precision while maintaining process feasibility through parameter optimization
Solution Approach 2:
The patent introduces a catalyst metal layer (containing Cu, Ni, Fe, Co, Pt, or Ru) as an intermediary substance that facilitates nanowire formation during evaporation deposition, enabling precise control over nanowire growth while simplifying the overall manufacturing process through this mediating catalytic layer
2Reliability
If next-generation nanowire-based semiconductor devices are developed, then device performance and uniformity are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent employs periodic control of deposition time (10-30 minutes) and temperature (340-420°C) during evaporation to achieve uniform nanowire formation across large areas, ensuring consistent device performance while managing process complexity through rhythmic, controlled deposition cycles
Solution Approach 2:
The patent creates nanowires with specific local properties (diameter 5-50 nm, length 1-10 μm) through localized evaporation deposition on the catalyst metal layer, achieving high device uniformity by controlling local nanowire characteristics while managing overall process complexity
3Manufacturing precision
If nanowires are formed through evaporation process with catalyst metal layer, then nanowire quality and device performance are enhanced, but manufacturing time and process steps are extended
Solution Approach 1:
The patent performs preliminary formation of the catalyst metal layer containing specific metals (Cu, Ni, Fe, Co, Pt, or Ru) before the actual nanowire deposition, which prepares the substrate to enable faster and more precise nanowire formation during the subsequent evaporation process, reducing overall manufacturing time while maintaining high precision
Solution Approach 2:
The patent optimizes the deposition time parameter to a specific range (10-30 minutes) at controlled temperature (340-420°C) to achieve precise nanowire formation without excessive process time, balancing manufacturing precision with time efficiency through parameter optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the direct formation of semiconductor devices with nanowires on insulating layers, enhancing device performance, uniformity, and facilitating large-area processing, potentially leading to more efficient and commercially viable semiconductor devices.
Implementation Method 1
The nanowire may be formed by using an evaporation process
Implementation Method 2
The nanowire may be formed by using an evaporation process
Implementation Method 3
The catalyst metal layer may include at least one of copper (Cu), nickel (Ni), iron (Fe), cobalt (Co), platinum (Pt), and ruthenium (Ru)
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3~4
AI summary
Provided are methods of forming nanostructures, methods of manufacturing semiconductor devices using the same, and semiconductor devices including nanostructures. A method of forming at least one nanostructure may include forming an insulating layer (N11) and forming at least one nanostructure (NW11) on the insulating layer. The insulating layer (N11) has a crystal structure and is a two-dimensional (2D) material, like hexagonal boron nitride (h-BN). The insulating layer may be formed on a catalyst metal layer (M11). The nanostructures may include at least one of silicon (Si), germanium (Ge), and SiGe. The nanostructure may include at least one nanowire and may be formed directly on the 2D insulating layer by evaporation. Devices may be formed that comprise a plurality of nanowires (NW11) in a network structure.