Nanowires Zone Reduces Thermal Stress on Chip Current Paths
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Solution Overview
Problem
Conventional chips are prone to damage from thermal stress caused by soldering and operation currents, leading to deformation, fracture, or lifting off the substrate, which is typically addressed by increasing the current path size, resulting in reduced chip density and increased manufacturing costs.
Innovation Solution
Surrounding the current path with nanowires structures that dissipate thermal stress, implemented through etching, electrochemical, or deposition processes, with depths ranging from 1 μm to 5 μm, to prevent damage and enhance operational life and rated current capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the current path is increased to prevent thermal stress damage, then the reliability of the current path is improved, but the number of chips per wafer is reduced and manufacturing cost increases
Solution Approach 1:
The patent applies local quality by creating nanowires zones with specific structural properties (depth 1-5 μm, wire diameter 50-200 nm) only in regions adjacent to current paths where thermal stress concentration occurs. This localized structural modification provides stress relief precisely where needed without requiring overall enlargement of current paths, thereby maintaining chip density while improving reliability.
Solution Approach 2:
The patent transitions from two-dimensional current path geometry to three-dimensional nanowires structures by etching vertical channels and filling them with conductive material. This dimensional change creates a complex 3D nanoscale structure that provides thermal stress management functionality without increasing the planar footprint, thus maintaining high chip per wafer count while improving current path reliability.
2Strength
If the size of the current path is increased to prevent thermal stress damage, then the current path can withstand higher thermal stress, but the manufacturing cost per chip increases
Solution Approach 1:
The patent changes physical parameters by introducing nanowires with specific depth (1-5 μm) and wire diameter (50-200 nm) to achieve thermal stress resistance. These parameter changes create a structure that provides strength enhancement at the nanoscale level, allowing standard-sized current paths to withstand thermal stress without requiring size increases that would raise manufacturing costs.
3Duration of action of stationary object
If nanowires structures are added to reduce thermal stress, then the operational life of the chip is prolonged, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the substrate into regions with nanowires zones adjacent to current paths. The nanowires themselves are segmented into discrete vertical structures with controlled depth and spacing. This segmented approach provides thermal stress relief functionality while maintaining a modular structure that can be integrated into existing chip designs without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nanowires structure effectively reduces thermal stress, preventing current path damage, prolonging chip life, increasing rated current, and allowing for smaller current path sizes, thus increasing chip density and reducing manufacturing costs.
Implementation Method 1
by surrounding the current path with nanowires structures to dissipate the thermal stress caused by a current flowing through the current path
Data Source
AI summary
A chip reducing thermal stress of current path thereon, including: a substrate having at least one nanowires zone formed on a surface thereof; and at least one current path formed within the at least one nanowires zone on the surface of the substrate, wherein, the at least one nanowires zone has a function of reducing a thermal stress of the at least one current path.