NarPar Interface for In-System Scan Testing
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Solution Overview
Problem
Conventional automated test equipment (ATE) for semiconductor testing is expensive, resource-intensive, and limits access for retesting after minor changes, preventing optimal design and testing in operational environments, leading to sub-optimal semiconductor quality and increased costs.
Innovation Solution
The implementation of a virtual automated test environment (VATE) system within the operating environment of integrated circuits, utilizing a novel narrow-parallel (NarPar) interface to perform scan-based testing without the need for external ATE, allowing for in-system testing and retesting with reduced resource constraints and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ATE is used for semiconductor testing, then scan-based testing can be performed, but the system becomes expensive and resource-intensive with limited access
Solution Approach 1:
The patent implements a virtual ATE system that creates a software-based simulation of automated test equipment. This virtual environment copies the essential testing capabilities of physical ATE while eliminating the need for expensive hardware infrastructure, thereby reducing system complexity and cost while maintaining scan-based testing quality
Solution Approach 2:
The invention replaces the mechanical/physical ATE system with a software-based virtual testing environment. This substitution eliminates the need for specialized laboratory equipment and reduces resource requirements while preserving the core functionality of scan-based semiconductor testing
2Reliability
If ATE testing is performed, then initial testing can be completed, but retesting after minor changes becomes impractical
Solution Approach 1:
The virtual ATE system is designed with dynamic adaptability, allowing test sequences to be automatically adjusted and regenerated in response to minor design changes. This dynamic reconfiguration capability enables efficient retesting without requiring complete test suite regeneration or manual intervention, thereby reducing retest time while maintaining comprehensive test coverage
3Reliability
If ATE is used, then testing can be performed in laboratory environment, but testing in operational environment is prevented
Solution Approach 1:
The virtual ATE system is designed as a universal testing platform that can operate across multiple environments including both laboratory and operational settings. This multi-functional capability allows the same virtual testing infrastructure to serve diverse testing scenarios, enabling scan-based testing to be performed in the actual operational environment where the semiconductor device will ultimately be deployed
4Reliability
If ATE testing is implemented, then initial testing can be done, but subsequent testing after installation cannot be performed
Solution Approach 1:
The virtual ATE system enables semiconductor devices to be tested autonomously in their operational environments without requiring external laboratory equipment. This self-service capability allows devices to undergo initial testing and subsequent retesting independently, eliminating the need for physical ATE access and enabling continuous testing throughout the device lifecycle
Data Source
AI summary
Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.