Narrow Active Pattern Semiconductor Device Gate Structure
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing delay time and improving performance while achieving higher integration and varying driving currents, particularly due to limitations in scaling and channel design.
Innovation Solution
The semiconductor device incorporates specific gate and active pattern structures with varying widths and heights, along with spacers, to optimize capacitance and resistance, thereby reducing delay time and enhancing performance and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate length is increased to improve current control capability, then the current control capability is improved, but the delay time increases and performance deteriorates
Solution Approach 1:
The patent transitions from planar 2D channels to three-dimensional channels (nanosheets, nanowires, multi-bridge structures) that extend in the vertical dimension. This allows the gate to control current through a 3D volume rather than a 2D surface, improving gate control capability without increasing gate length in the planar direction, thereby reducing delay time while maintaining reliability.
Solution Approach 2:
The gate structure completely surrounds the channel structure in three dimensions (top, bottom, and sidewalls), creating a nested configuration where the gate envelops the active region. This wraparound gate configuration provides superior electrostatic control compared to conventional planar gates, enabling better current control without increasing gate length.
2Productivity
If scaling is performed to increase device density, then the degree of integration is improved, but the manufacturing precision requirements increase
Solution Approach 1:
By utilizing the vertical dimension for channel formation (stacked nanosheets, multi-bridge channels), the patent achieves higher device density within the same footprint without requiring proportionally tighter lateral dimensions. This vertical stacking approach increases integration while maintaining more relaxed lateral fabrication tolerances compared to planar scaling.
3Productivity
If the active pattern width is reduced to improve integration, then the degree of integration is improved, but the driving current decreases
Solution Approach 1:
The patent compensates for reduced lateral width by increasing the vertical dimension of the channel (multiple stacked nanosheets or taller nanowires). This vertical expansion maintains the effective channel area and driving current capability while reducing the lateral footprint, thereby achieving higher integration without sacrificing power.
Solution Approach 2:
The channel structure utilizes composite configurations combining multiple semiconductor materials or layered structures (nanosheets stacked vertically, multi-bridge channels with different materials) to maintain high carrier mobility and driving current in the vertical direction even when lateral dimensions are reduced for higher integration.
Data Source
AI summary
Semiconductor devices are provided. A semiconductor device includes a gate structure extending in a first direction. The semiconductor device includes an active pattern intersecting the gate structure and having a width in the first direction and a height in a second direction. The width is smaller than the height. Moreover, the semiconductor device includes a source/drain region electrically connected to the active pattern.