Narrow Bezel Display Using Integrated GIP Driver and Boosting Capacitor

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Solution Overview

Problem

Existing flat panel displays face limitations in minimizing the bezel area due to the increased number of GIP elements required for high-resolution displays, which restricts the reduction of the non-display area and thus the bezel size.

Innovation Solution

A flat panel display design with a GIP type gate driver that includes a substrate with a pull-up thin film transistor and a boosting capacitor, where the boosting capacitor has a light shielding layer connected to the gate electrode and overlapping with the source electrode but not the drain electrode, along with a semiconductor layer and intermediate insulating layer configuration, to reduce the bezel area by minimizing the number of GIP elements and incorporating storage capacitance for stable signal generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of GIP elements is increased to support high resolution display, then the display resolution is improved, but the non-display area is increased and the bezel size cannot be reduced

Engineering Contradiction:
Improvedisplay resolutionVSAvoidnon-display area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent combines the gate driver circuit and storage capacitor into a single integrated GIP element structure. The gate driver transistor and storage capacitor share common electrodes and are formed in the same non-display area, reducing the total area required compared to separate implementations. This merging allows high resolution support with fewer discrete elements while minimizing the non-display area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent utilizes vertical stacking in the non-display area by forming the storage capacitor with overlapping electrodes in the vertical dimension. The gate electrode and storage capacitor electrodes are positioned at different vertical levels with insulating layers between them, effectively using the third dimension (height/thickness) to accommodate multiple functional elements without increasing the planar footprint, thus reducing the bezel area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If the GIP type gate driver is used to reduce manufacturing cost and simplify processes, then the manufacturing complexity is reduced, but the bezel area cannot be minimized due to the number of GIP elements required

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidbezel area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The gate driver circuit and storage capacitor are merged into a single integrated structure formed using the same thin film transistor fabrication process. This consolidation reduces the number of discrete components and simplifies the manufacturing process while minimizing the total non-display area required, thereby reducing the bezel size.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The GIP element structure serves multiple functions simultaneously: the gate driver transistor provides switching functionality while the integrated storage capacitor maintains charge. This multi-functional design eliminates the need for separate driver and capacitor components, simplifying manufacturing and reducing the bezel area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If the boosting capacitor is formed with light shielding layer overlapping the drain electrode, then the capacitance is increased, but the parasitic capacitance increases and affects signal stability

Engineering Contradiction:
Improvesignal stabilityVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The light shielding layer is selectively positioned to overlap only with the source electrode and channel area of the gate driver transistor, while deliberately avoiding overlap with the drain electrode. This localized configuration provides the necessary capacitance for signal stability while minimizing parasitic capacitance that would arise from extensive overlapping, thereby maintaining signal integrity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The light shielding layer, which could potentially create parasitic capacitance if positioned incorrectly, is strategically configured to provide beneficial capacitance enhancement through controlled overlapping with the source electrode while avoiding the drain electrode. This converts what could be a harmful effect (parasitic capacitance) into a beneficial one (signal stability) through careful geometric design.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design achieves a significantly narrower bezel area compared to IC type drivers, while ensuring stable gate driving signals, thereby enhancing the display's aesthetic appeal and operational efficiency.

Implementation Method 1

a light shielding layer connected to the first gate electrode and overlapping with the first source electrode

Methodology Applied
Scientific EffectLight shielding: Absorption (EM radiation)

Data Source

PatentEP3276410B1Display having narrow bezel
Publication Date: 2020.06.17 LG DISPLAY CO LTD
  • EP3276410B1 patent drawingFigure 1
  • EP3276410B1 patent drawingFigure 2
  • EP3276410B1 patent drawingFigure 3

AI summary

The present disclosure relates to a display having a narrow bezel structure. The present disclosure provides a flat panel display comprising: a substrate including a display area and a non-display area; a pull-up thin film transistor including a first gate electrode, a first source electrode and a first drain electrode, disposed in the non-display area; and a boosting capacitor disposed between the first gate electrode and the first source electrode; wherein the boosting capacitor includes a light shielding layer connected to the first gate electrode and overlapping with the first source electrode, but not overlapping with the first drain electrode.