Narrow Bezel LCD Array Substrate with Auxiliary Lines
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Solution Overview
Problem
Current liquid crystal display (LCD) devices have a wide bezel due to the significant non-display areas on the sides, which hinders their slimness and lightness, particularly in applications like TVs and monitors, where a narrower bezel is desired.
Innovation Solution
The design of an array substrate for LCD devices with a narrower bezel is achieved by reducing the width of the third and fourth non-display areas by eliminating the gate PCB and FPC in these areas and using multi-layered auxiliary lines for electrical connections, maintaining the aperture ratio and allowing for a more compact structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If gate PCB and FPC are installed in the third and fourth non-display areas, then electrical connections are maintained, but the bezel width increases
Solution Approach 1:
The patent extracts and removes the gate PCB and FPC from the third and fourth non-display areas, eliminating the components that cause bezel width increase while maintaining electrical connections through alternative routing paths in the first and second non-display areas
Solution Approach 2:
The patent redistributes electrical connection paths from horizontal routing (across the width where gate PCB and FPC would be installed) to vertical routing (through the first and second non-display areas), effectively moving the connection dimension to reduce bezel width in the horizontal direction
2Length of moving object
If the third and fourth non-display areas are reduced, then the bezel becomes narrower, but electrical connection paths are limited
Solution Approach 1:
The patent merges the electrical connection functions into the first and second non-display areas, combining multiple connection paths (gate lines and data lines) through shared routing regions, thereby reducing overall structural complexity despite narrower bezel constraints
3Shape
If gate PCB and FPC are removed from third and fourth non-display areas, then the device becomes slimmer and lighter, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary routing design of gate lines and data lines through the first and second non-display areas during the array substrate manufacturing process, establishing connection paths before final assembly, thereby simplifying the overall manufacturing process despite the reconfigured layout
Data Source
AI summary
An array substrate for a narrow bezel type liquid crystal display device and method of manufacturing the same are provided. The array substrate includes: gate lines (GLs) on a substrate, the substrate including a display area and first to fourth non-display areas at respective sides, pixel regions, a gate insulating layer (GIL) on the GLs, a plurality of data lines on the GIL and crossing the GLs, a plurality of gate auxiliary lines parallel to the data lines and connected to respective GLs, an auxiliary line in the third non-display area with a first layer under the GIL and a second layer on the GIL, the first layer contacting the second layer through a first auxiliary contact hole in the GIL, a thin film transistor in each pixel region and connected to the GLs and data lines, and a pixel electrode connected to each thin film transistor.