Narrow Conductive Structures for Gate Contact in Integrated Circuits
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further miniaturization beyond the 10 nanometer node, and requires new methodologies to optimize device performance and increase edge placement error margin.
Innovation Solution
The implementation of narrow conductive structures for gate contact or trench contact, involving recessing of gate structures, dielectric liner formation, and conductive material deposition, allows for greater scaling and reduced etch requirements, enabling edge placement error margin expansion and efficient contact formation over active gate regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node and below
Solution Approach 1:
The fabrication process is divided into distinct stages: forming dielectric spacers, recessing gate structures, depositing dielectric liners, and filling conductive materials. Each stage addresses specific precision requirements independently, allowing conventional processes to be extended to 10nm node through systematic breakdown of the fabrication sequence.
Solution Approach 2:
Dielectric spacers are formed in advance before gate structure recessing, establishing precise dimensional boundaries that guide subsequent etching and deposition steps. This preliminary structuring enables accurate feature placement at 10nm scale without requiring entirely new fabrication methodologies.
2Manufacturing precision
If gate structures are recessed to enable narrow conductive structures, then edge placement error margin increases, but device complexity increases
Solution Approach 1:
Dielectric liners are deposited as intermediary layers between the recessed gate structures and the conductive fill materials. These liners provide a controlled interface that simplifies the overall process by preventing direct interaction between the gate structure and conductive material, thereby reducing structural complexity while maintaining edge placement error margin benefits.
Solution Approach 2:
The gate structures are recessed only in specific regions where narrow conductive structures are required, while maintaining full depth in other areas. This localized modification increases edge placement error margin where needed without unnecessarily complicating the entire device structure.
3Manufacturing precision
If conductive material is deposited to form narrow structures, then metal volume over gates is reduced for capacitance reduction, but manufacturing precision requirements increase
Solution Approach 1:
The dielectric spacers and liners serve as self-aligned masks and guides that automatically define the boundaries of narrow conductive structures during deposition. This self-service approach ensures precise dimensional control of conductive structures without requiring additional alignment steps, thereby maintaining ease of manufacture while achieving the required precision.
4Manufacturing precision
If new methodologies are introduced for 10 nanometer node fabrication, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The dielectric spacer structure serves multiple functions: it acts as a mask for gate recessing, defines the width of narrow conductive structures, and provides a platform for dielectric liner deposition. This multi-functionality allows a single structural element to address multiple precision requirements, thereby improving manufacturing precision without proportionally increasing device complexity.
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2
AI summary
Narrow conductive via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. A dielectric liner is along the plurality of dielectric spacers over the plurality of gate structures. A plurality of conductive pin structures is between the dielectric liner, individual ones of the plurality of conductive pin structures on corresponding ones of the plurality of gate structures.