Narrow DRAM Channel Systems with Shared Control Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory storage systems, such as DRAM and DDR systems, face inefficiencies due to fixed access granularities and poor data locality characteristics, leading to wasted resources and suboptimal performance, especially in applications with smaller data sizes and poor data access patterns.
Innovation Solution
A customizable memory controller system with multiple narrow memory channels and shared communication lines, utilizing auto-precharge commands to optimize command/data bus utilization and enable independent, concurrent control of memory channels, thereby improving access efficiency and reducing resource wastage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional DRAM systems use fixed cache line access granularity (64 Bytes), then memory interface width standards are maintained, but applications with smaller data sizes experience resource wastage and poor access efficiency
Solution Approach 1:
The patent divides the conventional wide memory interface into multiple narrow channels (e.g., splitting a 64-bit interface into four 16-bit channels). Each narrow channel can be independently activated based on the actual data access size, allowing applications with smaller data footprints to use only the necessary portion of the memory interface, thereby reducing resource wastage and improving access efficiency for such applications.
2Quantity of substance
If conventional memory systems use wide memory channels, then data transfer bandwidth is high, but applications with poor locality characteristics suffer from accessing unused data
Solution Approach 1:
The patent implements dynamic channel activation where narrow memory channels are selectively enabled or disabled based on the actual access pattern and data size requirements of running applications. This dynamic configuration allows the memory subsystem to adapt to varying data utilization needs, activating only the necessary channels to avoid accessing and processing unused data, thereby improving effective data utilization and reducing energy consumption.
3Productivity
If multiple memory channels are introduced to improve access efficiency, then resource utilization improves, but system complexity and address pin overhead increase
Solution Approach 1:
The patent merges the control and addressing functions for multiple narrow channels into a unified controller architecture. The memory controller dynamically multiplexes control signals and address lines across the narrow channels, allowing multiple channels to share common command/address buses. This merging approach enables efficient multi-channel operation while minimizing the increase in address pin overhead and control complexity compared to having fully independent wide channels.
Data Source
AI summary
The systems and methods are configured to efficiently and effectively access memory. In one embodiment, a memory controller comprises a request queue, a buffer, a control component, and a data path system. The request queue receives memory access requests. The control component is configured to process information associated with access requests via a first narrow memory channel and a second narrow memory channel. The first narrow memory channel and the second narrow memory channel can have a portion of command/control communication lines and address communication lines that are included in and shared between the first narrow memory channel and the second narrow memory channel. The data path system can include a first data module and one set of unshared data lines associated with the first memory channel and a second data module and another set of unshared data lines associated with second memory channel.