Narrow Mask Lightly Doped Drain for Transistor Leakage Control
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Solution Overview
Problem
In semiconductor devices, particularly solid-state imaging devices, the formation of a lightly doped drain region outside the gate electrode width can lead to leakage current paths, causing short circuits and decreased threshold voltages in transistors, especially when using isolation methods like shallow trench isolation (STI) or diffusion layers.
Innovation Solution
A method is developed where a lightly doped drain region is formed only near the surface of the semiconductor substrate in a region narrower than the gate electrode width, using a mask pattern with an opening narrower than the gate electrode, to prevent leakage current paths and ensure proper transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is performed using a mask with an opening wider than the gate electrode to form a lightly doped drain region, then transistor noise characteristics are improved, but leakage current paths are created outside the gate electrode width causing short circuits and decreased threshold voltage
Solution Approach 1:
The patent applies local quality by forming the lightly doped drain region only in specific locations (inside the gate electrode width) rather than uniformly across the entire source/drain region. This is achieved by using a mask with an opening width equal to or narrower than the gate electrode width, ensuring that the lightly doped drain region is created only where needed for noise reduction while avoiding leakage current paths outside the gate electrode.
Solution Approach 2:
The patent uses partial action by forming the lightly doped drain region only in the necessary area (within the gate electrode width) rather than throughout the entire source/drain region. The mask opening is deliberately made equal to or narrower than the gate electrode width to provide just enough lightly doped drain region for noise reduction without extending into isolation regions where it would create leakage paths.
2Manufacturing precision
If shallow trench isolation is used to increase device density, then isolation precision is improved, but crystal defects due to thermal stress occur because of the difference in coefficient of thermal expansion between the deeply buried silicon dioxide layer and the silicon substrate
Solution Approach 1:
The patent changes the parameter of isolation depth by using diffusion layer isolation instead of deeply burying the silicon dioxide layer. The diffusion layer isolation forms the isolation region by diffusing impurities into the semiconductor substrate, creating a shallower isolation structure that reduces thermal stress while still providing effective electrical isolation between devices.
3Object-affected harmful factors
If a p+ region is formed at the boundary between the silicon dioxide layer and the photodiode to prevent dark current, then dark current is reduced, but the photodiode area is narrowed leading to decreased saturation signal amount and sensitivity
Solution Approach 1:
The patent replaces the permanent, area-consuming p+ region with a more efficient isolation mechanism. By using diffusion layer isolation with proper doping profiles, the need for additional p+ regions at the photodiode boundary is reduced or eliminated, as the diffusion layer itself provides the necessary isolation and carrier sweep-out function without occupying additional photodiode area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents leakage current paths and short circuits, improving transistor characteristics by reducing noise and maintaining threshold voltage stability, while also avoiding the reduction in photodiode area that can occur with traditional methods.
Implementation Method 1
forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask
Data Source
AI summary
A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.