Narrow Mesa IGBT with Segmented Active and Inactive Trenches

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Solution Overview

Problem

Conventional IGBT devices with narrow mesa structures face the challenge of collector-induced barrier lowering (CIBL), which increases saturation current and weakens short circuit resistance, limiting their performance.

Innovation Solution

The IGBT device features active and inactive trench structures with a unique arrangement, where the active gate trench structures and inactive emitter trench structures are alternately arranged, and the inactive emitter injection regions are formed above well regions, eliminating the P-type doping region from the active mesa and incorporating it in the inactive mesa, enhancing electron density and reducing on-resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a narrow mesa structure is introduced to reduce on-resistance, then electron density and injection efficiency are enhanced, but collector induced barrier lowering (CIBL) occurs which increases saturation current and weakens short circuit resistance

Engineering Contradiction:
Improveshort circuit resistanceVSAvoidcollector induced barrier lowering (CIBL)
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The device is divided into active mesa regions (between active gate trenches) and inactive mesa regions (between inactive emitter trenches). The P-type doping region is selectively placed only in the inactive mesa regions, while the active mesa regions remain undoped. This segmentation allows the active mesa to maintain high electron density without holes that would cause CIBL, while the inactive mesa provides necessary doping for device operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the device are given different doping characteristics. The active mesa regions have undoped or lightly-doped characteristics to maximize electron density and eliminate CIBL, while the inactive mesa regions have P-type doping to provide hole concentration where needed. This local differentiation of material properties resolves the contradiction between reducing on-resistance and preventing CIBL.

Inventive Principle:
Principle #3Local quality

2Reliability

If conventional narrow mesa IGBT structure is used, then on-resistance is reduced through enhanced electron density, but saturation current increases due to CIBL effect

Engineering Contradiction:
Improveon-resistanceVSAvoidsaturation current increase
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The device is divided into active mesa regions (between active gate trenches) and inactive mesa regions (between inactive emitter trenches). The P-type doping region is selectively placed only in the inactive mesa regions, while the active mesa regions remain undoped. This segmentation allows the active mesa to maintain high electron density without holes that would cause CIBL, while the inactive mesa provides necessary doping for device operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the device are given different doping characteristics. The active mesa regions have undoped or lightly-doped characteristics to maximize electron density and eliminate CIBL, while the inactive mesa regions have P-type doping to provide hole concentration where needed. This local differentiation of material properties resolves the contradiction between reducing on-resistance and preventing CIBL.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11677019B2IGBT device with narrow mesa and manufacture thereof
Publication Date: 2023.06.13 SIEN (QINGDAO) INTEGRATED CIRCUITS CO LTD
  • US11677019B2 patent drawing
  • US11677019B2 patent drawing
  • US11677019B2 patent drawing

AI summary

The present application provides an insulated gate bipolar transistor (IGBT) device with narrow mesa and a manufacture thereof. The device comprises: a semiconductor substrate; gate trench structures and emitter trench structures formed on front surface of the semiconductor substrate and alternately arranged along with horizontal direction; wherein the gate trench structures and the emitter trench structures are respectively set in pair along with the arrangement direction, and the pairs of the gate trench structures and the pairs of the emitter trench structures are set in alternate arrangement along with the arrangement direction; well regions formed between the emitter trench structures of one pair; emitter injection regions formed between the gate trench structures of one pair and between the emitter trench structures of one pair, respectively; and wherein, in the region between the emitter trench structures of the one pair, the emitter injection region is above the well region.