Narrow Shifter FFMA Operations Using Composite Register Segmentation
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Solution Overview
Problem
Existing fused floating-point multiply-add (FFMA) operations in graphics processing units (GPUs) require a wide shifter that incurs significant power consumption when switching between FFMA and multiply-only operations, as the C operand must be set to zero, leading to inefficient power usage.
Innovation Solution
A method that uses a narrow shifter and composite register to perform FFMA operations, allowing the shifter logic to be gated off in multiply-only mode, eliminating the need to load or overwrite previous values, thereby reducing power consumption and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a wide shifter is used to accommodate all exponent value cases in FFMA operations, then the shifter can handle both full left and full right shifts, but the shifter size becomes more than four times the width of the operands, increasing power consumption and device complexity
Solution Approach 1:
The shifter is divided into multiple segments or portions, each handling specific shift ranges. The composite register is also segmented into multiple portions that can be independently activated. This segmentation allows the system to use only the necessary shifter segments for each operation, reducing the active shifter width and power consumption while maintaining the ability to handle all exponent value cases.
Solution Approach 2:
The shifter width is made dynamic rather than static. The system activates only the necessary portions of the shifter and composite register based on the specific operation requirements. This dynamic activation reduces the effective shifter width during different operation modes, lowering power consumption and complexity while maintaining full adaptability.
2Reliability
If the C operand is set to zero for multiply-only operations, then the operation can proceed correctly, but all shifter registers must be overwritten to flush prior values, incurring significant power consumption
Solution Approach 1:
The shifter flushing operation is extracted and eliminated for multiply-only modes. By using separate portions of the composite register and selectively activating shifter portions, the system avoids the need to flush shifter registers when performing multiply-only operations, thereby eliminating the associated power consumption while maintaining operational correctness.
Solution Approach 2:
Different qualities or activation states are applied to different portions of the composite register. Some portions are activated for FFMA operations while others remain inactive or retain previous values for multiply-only operations. This local differentiation allows the system to perform correct operations without unnecessary register flushing, reducing power consumption.
3Measurement precision
If a wide shifter is used to ensure proper alignment of the C operand in FFMA operations, then the addition can be performed correctly, but the shifter requires larger size and more power consumption
Solution Approach 1:
The shifter is segmented into multiple portions that can be independently activated based on the alignment requirements of the specific operation. This segmentation allows the system to activate only the necessary shifter width for proper operand alignment, maintaining measurement precision while reducing power consumption by keeping unused segments inactive.
Data Source
AI summary
A fused floating-point multiply-add element includes a multiplier that generates a product, and a shifter that shifts an addend within a narrow range. Interpreting logic analyzes the magnitude of the addend relative to the product and then causes logic arrays to position the shifted addend within the left, center, or right portions of a composite register depending in the magnitude of the addend relative to the product. The interpreting logic also forces other portions of the composite register to zero. When the addend is zero, the interpreting logic forces all portions of the composite register to zero. Final combining logic then adds the contents of the composite register to the product.