Native-Gate Quantum Circuit Synthesis for Lower Error and Runtime
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing quantum compilers face challenges in synthesizing quantum circuits efficiently using sequences of gates available on quantum computers, particularly with fractional CNOT gates, leading to suboptimal execution times and increased error rates.
Innovation Solution
A method for synthesizing quantum circuits using a classical computer to determine a group of quantum circuits formed from native qubit gates that perform a target operation on a quantum computational device, optimizing a cost function based on performance criteria such as infidelity and operation count, and selecting the most suitable circuit based on these criteria.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If quantum circuits are synthesized using standard decomposition methods with CNOT and single-qubit rotations, then the target operation can be implemented, but the execution time increases and error rates increase due to more pulses required
Solution Approach 1:
The patent changes the parameter space by introducing fractional CNOT gates (CNOT^α) where α is a continuous parameter. This allows the synthesis to find optimal gate sequences that minimize both execution time and error rates by adjusting the fractional parameter α, rather than being constrained to standard integer-based gate decompositions.
Solution Approach 2:
The patent makes the gate set dynamic by allowing the quantum compiler to select from a continuous family of fractional CNOT gates based on the specific target operation and hardware characteristics. This dynamic selection enables adaptive optimization of circuit depth and error rates for different compilation scenarios.
2Productivity
If a parametric family of fractional CNOT gates is exposed to users, then more optimal circuits can be synthesized, but the device complexity and ease of operation deteriorate due to the complexity of managing parametric gates
Solution Approach 1:
The quantum compiler performs self-service by automatically selecting and optimizing fractional CNOT gate parameters based on the target operation and hardware characteristics. This eliminates the need for users to manually manage the complexity of parametric gates while still benefiting from the optimized gate sequences.
Solution Approach 2:
The patent introduces an intermediary layer (the quantum compiler) that translates high-level quantum operations into optimized sequences of fractional CNOT gates. This intermediary handles the complexity of parametric gate management, shielding users from the intricacies while enabling productive compilation.
3Manufacturing precision
If more pulses are used in quantum circuit execution, then the quantum operations can be more accurately implemented, but the execution time increases and error rates increase
Solution Approach 1:
By changing to fractional CNOT gates with optimized parameter α, the patent achieves accurate quantum operations with fewer pulses. The continuous parameter α allows fine-tuning of the gate operation to match the target unitary transformation more efficiently, reducing the total pulse count while maintaining accuracy.
Data Source
AI summary
A method for a classical computer to synthesize a quantum circuit for use on a quantum computational device includes receiving information for a target operation to be implemented on said quantum computational device, and receiving information regarding native qubit gates that are available on said quantum computational device to be used to implement said quantum circuit; The method further includes determining each of a plurality of quantum circuits formed from said native qubit gates such that each of said plurality of quantum circuits will perform a function substantially equivalent to said target operation when implemented on the quantum computational device. The method further includes selecting one of said plurality of quantum circuits formed from said native qubit gates, based on a performance criterion of said quantum computational device.