Direct-Bonded Native Interconnects for Low-Power Chiplet Integration
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Solution Overview
Problem
Conventional microelectronic systems require complex and power-hungry standard interfaces for chip-to-chip communication, leading to increased size, cost, and heat generation due to the need for standard pinout geometry, serialization, and voltage leveling, which are often unnecessary for the actual utilization of chip functionality.
Innovation Solution
Direct-bonded native interconnects between dies eliminate the need for standard interfaces by forming metal-to-metal bonds between native conductors, allowing for short data paths and two-way communication, enabling efficient signal transfer and reducing power requirements through the use of an active base die that can adapt multiple interconnect types and accommodate diverse chiplets with different operating voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard interfaces are used for chip-to-chip communication, then compatibility and standardized protocols are achieved, but device size, power consumption, and heat generation increase
Solution Approach 1:
The patent extracts and eliminates the standard interface layer from the communication path between chips. By directly bonding native conductors from one chip to another, the patent removes the intermediary standard interface components (serialization logic, voltage level shifters, ESD protection circuits) that traditionally enabled compatibility, thereby reducing power consumption while maintaining functional connection.
Solution Approach 2:
The patent applies asymmetry by allowing each chip to use its own native interface standards and signaling protocols independently. Instead of forcing both chips to conform to a common standard, the system enables asymmetric connections where Chip A's native outputs directly drive Chip B's native inputs, with each chip maintaining its own standardized interface requirements.
2Adaptability or versatility
If standard interfaces with pinout geometry and serialization are used, then interoperability is enabled, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the standard interface logic layer that introduces complexity. By eliminating serialization/deserialization blocks, protocol encoding/decoding logic, and interface control circuits, the patent reduces device complexity while maintaining the ability to interoperate through direct native signal connections.
Solution Approach 2:
Instead of the conventional approach where chips adapt to standard interfaces, the patent inverts the model by having standard interfaces adapt to chip native signals. The system allows native conductors to connect directly without modification, reversing the traditional adaptation direction and reducing the complexity burden on individual chips.
3Reliability
If standard interfaces with voltage leveling and ESD protection are implemented, then signal robustness is improved, but power consumption and device size increase
Solution Approach 1:
The patent extracts and removes voltage level shifting circuits and ESD protection structures from the interface path. By directly bonding native conductors, the patent eliminates these auxiliary components that occupy significant die area, accepting that native signals maintain sufficient robustness for direct connections without additional protection layers.
4Adaptability or versatility
If standard interfaces are used, then multiple independent chips can communicate, but heat generation and power requirements increase
Solution Approach 1:
The patent removes the power-hungry standard interface components that generate heat during multi-chip communication. By eliminating serialization logic, voltage level conversion circuits, and protocol management hardware, the patent reduces the thermal load while maintaining the ability to communicate across multiple chips through direct native conductor bonds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the size and power consumption of microelectronic devices, enhances signal quality and timing, and allows for more efficient integration of chiplets in smaller, faster, and more power-efficient architectures, such as ASIC, ASSP, and FPGA, while supporting dual or quad data rate operations.
Implementation Method 1
The native interconnects are metal-to-metal bonds formed directly between native conductors of a die and conductors of a second die
Data Source
AI summary
Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.