Native MOS Transistor Biasing for CMOS Leakage Reduction

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Solution Overview

Problem

Modern integrated circuits (ICs) face increased power consumption due to gate-induced drain leakage (GIDL) currents, which are particularly pronounced in low-power modes of operation, leading to higher overall leakage and power consumption.

Innovation Solution

The implementation of CMOS circuitry with native MOS transistors coupled to supply bias voltages to reduce GIDL currents in p-channel and n-channel transistors, thereby minimizing the voltage between the drain and gate, which reduces leakage currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of transistors in CMOS circuitry is increased to enhance functionality, then the complexity and capability of the IC are improved, but the power consumption increases due to increased leakage currents

Engineering Contradiction:

ImprovefunctionalityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent applies different threshold voltage characteristics to different transistor types within the CMOS circuit. Native transistors with zero threshold voltage are used specifically for leakage reduction paths, while standard transistors maintain normal switching functionality. This local differentiation allows the circuit to reduce overall leakage current without sacrificing the functionality provided by the increased transistor count.

Inventive Principle:

Principle #3Local quality

2Ease of manufacture

If standard CMOS transistors are used to implement circuit functionality, then the circuit can operate with standard fabrication processes, but GIDL currents increase power consumption especially in low-power modes

Engineering Contradiction:

Improvefabrication process compatibilityVSAvoidleakage current

Core Design Contradiction:

Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent combines two types of transistors with different characteristics: standard CMOS transistors for normal operation and native transistors with zero threshold voltage for leakage reduction. This composite approach allows the circuit to benefit from both the manufacturability of standard processes and the low-leakage properties of native transistors, effectively reducing GIDL currents while maintaining fabrication compatibility.

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces GIDL currents, leading to lower power consumption and improved performance in both normal and low-power modes of operation, as demonstrated by simulation results showing significant reductions in GIDL current contributions.

Implementation Method 1

at least one p-channel transistor having a gate-induced drain leakage (GIDL) current

Methodology Applied

Scientific EffectGate-induced drain leakage (GIDL):

Data Source

PatentUS11646735B2Apparatus with electronic circuitry having reduced leakage current and associated methods

Publication Date: 2023.05.09 SILICON LABORATORIES INC

AI summary

An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.