Native NMOS Antifuse Threshold Voltage Reduction

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Solution Overview

Problem

One-time programmable memories (OTPs) face high power consumption due to internal design requirements, particularly related to voltage level needs for NMOS transistors, which result in voltage drops that hinder efficient operation and verification of antifuses.

Innovation Solution

Implementing native NMOS antifuses by blocking the threshold implant during the NMOS fabrication process, eliminating the threshold voltage and allowing for lower supply voltages, thereby reducing power consumption and facilitating easier programming and verification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional NMOS transistors are used in OTP fabrication, then proper forward biasing of the transistor is achieved, but voltage drop across gate to drain increases power consumption

Engineering Contradiction:

Improveproper forward biasingVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the threshold voltage parameter of the NMOS transistor by blocking the threshold implant step during fabrication. This creates a native NMOS transistor with near-zero threshold voltage, eliminating the voltage drop issue while maintaining proper forward biasing capability.

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If threshold implant is performed during NMOS fabrication, then standard NMOS transistor characteristics are achieved, but verification of antifuse state becomes difficult due to threshold voltage interference

Engineering Contradiction:

Improvestandard NMOS fabricationVSAvoidantifuse verification

Core Design Contradiction:

Ease of manufactureVSDifficulty of detecting and measuring

Solution Approach 1:

The patent extracts or removes the threshold voltage characteristic from the NMOS transistor by blocking the threshold implant step. This elimination of the interfering threshold voltage allows clear verification of the antifuse state without signal masking.

Inventive Principle:

Principle #2Taking out (Extraction)

3Use of energy by moving object

If native NMOS antifuses are implemented by blocking threshold implant, then threshold voltage is minimized and power consumption is reduced, but fabrication process complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoidfabrication process

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

Instead of following the conventional approach of performing threshold implant and then trying to manage its effects, the patent inverts the approach by deliberately blocking the threshold implant step. This reverse engineering approach simplifies the overall system behavior despite adding a process modification.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS7649798B2Memory device using antifuses

Publication Date: 2010.01.19 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.