Native NMOS Power Detector Circuit for Stable Reset Thresholds
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Solution Overview
Problem
Existing power-detection circuitries in electronic devices face challenges in accurately determining the validity of a power-supply voltage level, particularly in ensuring reliable operation during power-up stages when the voltage is unstable, and often require additional components like resistors and capacitors, which increase complexity and size.
Innovation Solution
A power-detection circuit comprising a native N-channel Metal-Oxide-Semiconductor (NMOS) transistor and a P-channel Metal-Oxide-Semiconductor (PMOS) transistor, where the gates and source of the NMOS transistor are grounded, and the drains of both transistors are connected to an output port, with the source of the PMOS transistor connected to the input voltage, generating an output voltage that remains zero below a threshold and converges to the input voltage above it, allowing for reliable reset signal generation without additional components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional resistors and capacitors are used in power-detection circuits, then measurement precision and reliability are improved, but device complexity and size increase
Solution Approach 1:
The patent extracts and eliminates unnecessary components (resistors and capacitors) from the power-detection circuit, using only the essential NMOS and PMOS transistors to achieve the detection function. This reduces device complexity while maintaining the core voltage detection capability through the transistor threshold voltage mechanism.
Solution Approach 2:
The circuit uses the intrinsic threshold voltage characteristics of the NMOS and PMOS transistors themselves as the reference for detection, rather than requiring external reference voltage circuits or additional components. The transistors' own physical properties provide the measurement reference, eliminating the need for separate reference voltage generation circuitry.
2Measurement precision
If additional resistors and capacitors are used in power-detection circuits, then measurement precision is improved, but the circuit size increases
Solution Approach 1:
The patent removes resistors and capacitors from the circuit design, retaining only the minimal necessary transistors. This extraction of non-essential components directly reduces the circuit area occupied by passive elements, while the active transistor area is optimized through the simple two-transistor configuration.
Solution Approach 2:
The detection function and reference voltage function are merged into the same transistor structures. The NMOS and PMOS transistors simultaneously serve as both the detection elements and the reference voltage sources, eliminating the need for separate reference voltage circuits and reducing overall circuit area.
3Reliability
If complex power-detection schemes are used, then reliability during power-up is improved, but ease of manufacture decreases
Solution Approach 1:
The circuit relies on the natural threshold voltage characteristics of standard NMOS and PMOS transistors, which are inherent properties of commonly available transistor devices. This self-service approach using intrinsic device properties simplifies manufacturing by eliminating the need for specialized components or complex biasing circuits, while ensuring reliable operation during power-up through the threshold voltage mechanism.
Solution Approach 2:
The patent utilizes the threshold voltage parameter of standard transistors as the detection reference, changing from external reference voltage schemes to intrinsic device parameter utilization. This parameter-based approach using standard transistor characteristics simplifies the manufacturing process while maintaining reliable voltage detection during power-up transitions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a compact, low-power, and robust power-detection circuit that ensures reliable reset signal generation by maintaining zero output voltage until the input voltage stabilizes above the threshold, reducing leakage current and eliminating the need for accurate reference voltages or calibration, thus enhancing the reliability and efficiency of power-up operations.
Implementation Method 1
the native NMOS transistor and the PMOS transistor are configured to produce at the output port, in response to the input voltage, an output voltage that is substantially zero when the input voltage is below a predefined threshold voltage, and converges to the input voltage when the input voltage exceeds the predefined threshold voltage
Data Source
AI summary
An electronic circuit includes a native N-channel Metal-Oxide-Semiconductor (NMOS) transistor and a P-channel Metal-Oxide-Semiconductor (PMOS) transistor. The gates of the native NMOS transistor and the PMOS transistor and the source of the native NMOS transistor are grounded. The drains of the native NMOS transistor and the PMOS transistors are connected to one another and to an output port, and the source of the PMOS transistor is connected to an input voltage.