Native PMOS Device with Strained Regions and High-k Gate
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Solution Overview
Problem
Conventional MOSFET devices experience degradation due to short channel effects, leading to instability in threshold voltage and reduced drive current as they are scaled down, necessitating a solution for maintaining low threshold voltage and high drive current over varying short channel lengths.
Innovation Solution
The native PMOS device incorporates a deep N-well, strained regions, and halo implants, along with a high-k gate oxide and metal gate, to enhance carrier mobility and control threshold voltage, while using CMOS logic foundry technology to improve processing efficiency and reduce heat-induced stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOSFET devices are scaled down to smaller dimensions to accommodate larger number of devices, then device density increases, but short channel effects cause degradation in threshold voltage stability and drive current
Solution Approach 1:
The patent introduces a deep N-well structure with specific doping concentrations that create localized electric field regions. The N-well is positioned at a depth of 0.5-2.0 micrometers below the substrate surface, creating a localized region that controls carrier distribution specifically in the channel region without affecting other parts of the device structure.
Solution Approach 2:
The patent modifies the doping concentration parameters in the N-well and substrate regions to optimize threshold voltage control. The N-well is doped with phosphorus or arsenic at concentrations of 1E16 to 1E18 atoms/cm³, while the substrate is doped at 1E15 to 1E17 atoms/cm³, creating specific electric field conditions that stabilize threshold voltage in short channel devices.
2Quantity of substance
If MOSFET devices are scaled down to smaller dimensions, then device density increases, but drive current decreases due to short channel effects
Solution Approach 1:
The deep N-well creates localized regions of high carrier concentration specifically in the channel area, enhancing carrier mobility where it is most needed for drive current while maintaining low doping concentrations in other regions to prevent harmful side effects.
Solution Approach 2:
The patent optimizes the doping concentration parameters and depth of the N-well to maximize carrier mobility in the channel region. By controlling the N-well depth at 0.5-2.0 micrometers and doping concentration at 1E16 to 1E18 atoms/cm³, the device achieves enhanced drive current despite the short channel length.
3Manufacturing precision
If conventional CMOS foundry technology is used with minimum design rules, then manufacturing precision is maintained, but processing complexity increases and heat-induced stress affects device performance
Solution Approach 1:
The patent separates the device structure into distinct functional regions: the deep N-well region for threshold voltage control, the channel region for carrier transport, and the source/drain regions for current injection. This segmentation allows each region to be optimized independently while maintaining compatibility with standard CMOS processing.
Solution Approach 2:
The deep N-well structure serves multiple functions simultaneously: it controls threshold voltage, enhances carrier mobility, and provides electrical isolation between adjacent devices. This multi-functionality reduces the need for additional processing steps while achieving multiple performance goals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a native PMOS device with higher drive current and stable low threshold voltage, effectively addressing short channel effects and maintaining performance across a range of channel lengths.
Implementation Method 1
A drive current, also referred to as a drain current, flows between the source and drain regions through the channel region when a gate potential above the threshold voltage is applied
Implementation Method 2
The conventional native PMSO device includes a P+ polysilicon gate, halo implants, lightly doped regions in the source and drain regions, and heavily doped regions in the source and drain regions
Implementation Method 3
The native PMOS device incorporates a deep N-well, strained regions, and halo implants, along with a high-k gate oxide and metal gate, to enhance carrier mobility
Data Source
AI summary
A native p-type metal oxide semiconductor (PMOS) device that exhibits a low threshold voltage and a high drive current over a varying range of short channel lengths and a method for fabricating the same is discussed in the present disclosure. The source and drain regions of the native PMOS device, each include a strained region, a heavily doped raised region, and a lightly doped region. The gate region includes a stacked layer of a gate oxide having a high-k dielectric material, a metal, and a contact metal. The high drive current of the native PMOS device is primarily influenced by the increased carrier mobility due to the strained regions, the lower drain resistance due to the raised regions, and the higher gate capacitance due to the high-k gate oxide of the native PMOS device.