NB-LDPC Error Correction Decoder for Fewer Decoding Iterations

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Solution Overview

Problem

Existing error correction systems using LDPC codes face inefficiencies due to the large number of iterations required for error correction decoding, leading to potential decoding failures and increased computational complexity.

Innovation Solution

An error correction decoder is implemented using a symbol generator, reliability value manager, flipping function value calculator, and symbol corrector to optimize the error correction process by updating reliability values based on C2V messages and calculating flipping function values to modify hard decision values, thereby reducing the number of iterations and improving decoding efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional LDPC decoding is used, then error correction can be performed, but the number of iterations required is large leading to decoding failures and increased computational complexity

Engineering Contradiction:
Improveerror correction capabilityVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the parameter representation from traditional bit-level to symbol-level (e.g., GF(4) field elements). By representing multiple bits as single symbols and performing operations in the Galois field, the decoding process achieves the same error correction capability with fewer iterations and reduced computational complexity per iteration.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent segments the data into non-binary symbols (e.g., grouping bits into 2-bit symbols for GF(4)) and processes them as unified units rather than individual bits. This segmentation allows the use of more powerful algebraic structures that provide better error correction performance with fewer decoding iterations.

Inventive Principle:
Principle #1Segmentation

2Reliability

If traditional LDPC decoding is used, then error correction can be performed, but the number of iterations required increases leading to potential decoding failures

Engineering Contradiction:
Improvedecoding success rateVSAvoidnumber of iterations
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

By changing from binary to non-binary parameter representation (e.g., GF(4) symbols), the patent achieves faster convergence in the decoding process. The symbol-level operations provide more information per iteration, reducing the total number of iterations needed to achieve successful decoding and improving the decoding success rate.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent substitutes the traditional bit-flipping mechanical process with algebraic operations in the Galois field. This substitution uses mathematical properties of finite fields to directly compute syndrome values and perform corrections, replacing iterative bit-flipping with more efficient field arithmetic that converges faster.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If NB-LDPC codes are used, then error correction capability is improved, but device complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses parameter changes to represent data in GF(q) fields where q>2, enabling more efficient error correction. By performing operations at the symbol level rather than bit level, the system achieves improved error correction capability while the algebraic structure of finite fields actually reduces the per-iteration computational complexity compared to binary approaches.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11031952B2Error correction decoder and memory system having the same
Publication Date: 2021.06.08 SK HYNIX INC
  • US11031952B2 patent drawing
  • US11031952B2 patent drawing
  • US11031952B2 patent drawing

AI summary

Provided herein may be an error correction decoder based on an iterative decoding scheme using NB-LDPC codes and a memory system having the same. The error correction decoder may include a symbol generator for assigning an initial symbol to a variable node, a reliability value manager for setting and updating reliability values of candidate symbols of the variable node in current iteration, a flipping function value calculator for calculating a flipping function value by subtracting a function value, related to the updated reliability values of remaining candidate symbols other than a target candidate symbol, from another function value, related to the updated reliability value of the target candidate symbol, in the current iteration, and a symbol corrector for changing the hard decision value to the target candidate symbol when the flipping function value is equal to or greater than a first threshold value in the current iteration.