NB-LDPC Error Correction Circuit for Hard-Error Decoding

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Solution Overview

Problem

Existing error correction techniques, particularly low-density parity-check (LDPC) codes, face inefficiencies in computational cycles and iterations due to hard errors, leading to potential decoding failures in memory systems.

Innovation Solution

An error correction circuit employing a Non-Binary Low Density Parity Check (NB-LDPC) code uses an iterative decoding scheme with a symbol configuration circuit, reliability value initialization, and symbol correction mechanisms to adjust variable node values based on threshold comparisons, enhancing decoding efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional LDPC codes are used for error correction, then error correction capability is provided, but computational cycles increase and decoding failures occur due to hard errors

Engineering Contradiction:

Improveerror correction capabilityVSAvoidcomputational cycles

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the fundamental parameter of the error correction code from binary LDPC to non-binary LDPC. This parameter change allows the decoder to process multiple bits per symbol, reducing the number of iterations needed for convergence while maintaining or improving error correction capability against hard errors

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If iterative decoding is performed to improve error correction, then decoding accuracy increases, but computational complexity increases

Engineering Contradiction:

Improvedecoding accuracyVSAvoidcomputational complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

By transitioning to non-binary LDPC codes, the patent changes the parameter of symbol representation, allowing each symbol to represent multiple bits. This reduces the number of iterative decoding steps required to achieve the same decoding accuracy, thereby reducing computational complexity while maintaining decoding precision

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent moves from binary decision spaces to multi-valued symbol spaces, effectively adding dimensionality to the decoding process. This dimensional change allows the decoder to resolve errors more efficiently by considering multiple bit combinations simultaneously, reducing the iterative complexity required

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10826531B2Error correction circuit and operating method thereof

Publication Date: 2020.11.03 SK HYNIX INC

AI summary

Provided herein may be an error correction circuit. An error correction circuit for performing error correction decoding based on an iterative decoding scheme using a NB-LDPC code may include a symbol configuration circuit for configuring an initial symbol to be assigned as a variable node value to a variable node, a reliability value initialization circuit for initializing first reliability values of candidate symbols corresponding to the variable node based on the initial symbol assigned to the variable node, and a symbol correction circuit updating the first reliability values of the candidate symbols based on communications received from a check node coupled to the variable node, the candidate symbols having updated first reliability values, respectively, and adjusting the variable node value to one of the candidate symbols based on a comparison with the updated first reliability value of one of the candidate symbols with a first threshold value.