NB-LDPC Check Node Decoding with Syndrome Decorrelation

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Solution Overview

Problem

Current methods for decoding non-binary Low-Density Parity-Check (LDPC) codes face high complexity and latency issues, particularly in hardware implementations, due to the complexity of check node computations in existing algorithms like the Extended Min-Sum (EMS) algorithm, which limits throughput and increases latency as the size of the Galois field grows.

Innovation Solution

A Syndrome-Based Check Node processing method is introduced, which allows for increased parallelism by generating syndromes from input elements with the highest reliability values and applying decorrelation to reduce the number of syndromes, enabling high throughput and low latency processing through massive parallel implementation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the Extended Min-Sum (EMS) algorithm is used for check node computation, then decoding accuracy is maintained, but hardware complexity and latency increase significantly

Engineering Contradiction:
Improvedecoding accuracyVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The check node computation is segmented into two distinct stages: syndrome computation stage and decorrelation stage. This segmentation allows each stage to be optimized independently, with the syndrome stage focusing on parallel computation and the decorrelation stage handling the remaining processing, thereby reducing overall hardware complexity while maintaining decoding accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The syndrome is computed preliminarily from all input messages before the final check node output is determined. This preliminary computation of the syndrome (sum of all inputs) allows subsequent decorrelation operations to be performed more efficiently, reducing the computational burden during the main decoding process and lowering hardware complexity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the Extended Min-Sum (EMS) algorithm is used for check node computation, then decoding accuracy is maintained, but latency increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

By segmenting the computation into parallel syndrome computation and sequential decorrelation stages, the patent reduces the critical path delay. The syndrome computation can be performed in parallel across multiple inputs simultaneously, reducing the time required compared to the traditional sequential EMS algorithm while maintaining the same decoding accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The syndrome is computed in advance as a preliminary step, allowing the decorrelation operations to proceed with pre-computed values. This preliminary action eliminates redundant computations that would otherwise increase latency, enabling faster convergence while preserving decoding performance.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If the size of the Galois field increases, then code capacity increases, but throughput decreases and latency increases

Engineering Contradiction:
Improvecode capacityVSAvoidthroughput
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments the check node computation to identify and exploit the syndrome computation pattern, which remains relatively independent of the Galois field size. By separating the syndrome computation (which scales better) from the decorrelation operations, the system can handle larger Galois fields with better throughput compared to traditional EMS implementation where all operations scale directly with field size.

Inventive Principle:
Principle #1Segmentation

4Quantity of substance

If the size of the Galois field increases, then code capacity increases, but hardware cost increases

Engineering Contradiction:
Improvecode capacityVSAvoidhardware cost
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

By segmenting the computation into syndrome and decorrelation stages, the patent reduces the hardware resources required for each stage. The syndrome computation stage uses simpler logic that scales better with Galois field size, and the decorrelation stage processes fewer values, overall reducing hardware cost while enabling larger code capacities.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10554226B2Method for controlling a check node of a NB-LDPC decoder and corresponding check node
Publication Date: 2020.02.04 CREONIC GMBH
  • US10554226B2 patent drawing
  • US10554226B2 patent drawing
  • US10554226B2 patent drawing

AI summary

Some embodiments are directed to a method for controlling a check node of a NB-LDPC decoder. The check node receives dc input lists Ui and delivers and delivers dc output lists Vi, with i∈[1 . . . dc]. Each input list and output list includes nm elements and each element of the input or output lists includes a reliability value associated to a symbol of a Galois Field GF(q) with q>nm. The input elements and output elements are sorted according to the reliability values in the lists. The method is a syndrome-based method. The syndromes are sums of dc elements of input lists Ui. The method includes a step of syndrome calculation, a step of decorrelation and a step for generating the output list.