NB-IoT HARQ Buffer Allocation for Parallel System Information Reception
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Solution Overview
Problem
In wireless communication networks, particularly in NB-IoT environments with weak signals or large coverage areas, the time required to successfully receive all system information messages is prolonged due to repeated receptions, leading to network registration delays for user equipment.
Innovation Solution
A wireless communication device with a buffer memory divided into HARQ buffer blocks and a MAC circuit that allocates HARQ processes for system information messages, enabling parallel reception from a base station during NB-IoT downlink scheduling periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If system information messages are received sequentially according to current NB-IoT specifications, then each message can be properly processed, but the time consumed to successfully receive all system information messages is significantly prolonged in weak signal environments
Solution Approach 1:
The patent segments the buffer memory into multiple HARQ buffer blocks, each capable of independently storing different system information messages. This segmentation enables parallel reception of multiple messages without requiring sequential processing, thereby reducing network registration time while maintaining reception reliability through dedicated buffer allocation for each message.
Solution Approach 2:
The patent introduces a new dimension of parallel processing by allocating multiple HARQ processes to receive system information messages simultaneously within the same downlink scheduling period. This transforms the traditional sequential reception approach into a parallel reception model, significantly reducing the time dimension for network registration while maintaining message integrity.
2Productivity
If multiple HARQ processes are allocated for parallel reception of system information messages, then network registration speed is improved, but device complexity increases
Solution Approach 1:
The buffer memory is segmented into multiple HARQ buffer blocks, with each block dedicated to storing specific system information messages. This segmentation allows the MAC circuit to manage multiple HARQ processes independently, improving network registration speed while keeping the complexity manageable through structured organization of buffer resources.
Solution Approach 2:
The HARQ buffer blocks are designed with multi-functionality to handle different types of system information messages (SIB1, SIB2, etc.) uniformly. Each buffer block can serve multiple purposes: storing initial messages, retaining retransmissions, and supporting different HARQ processes, thereby reducing overall device complexity through resource sharing.
Data Source
AI summary
A wireless communication device includes a buffer memory and a media access control (MAC) circuit. The MAC circuit is coupled to the buffer memory, and is configured to divide the buffer memory according to system information messages required by the wireless communication device, such that the buffer memory includes hybrid automatic repeat request (HARQ) buffer blocks, and assign HARQ processes for the system information messages required by the wireless communication device, so as to receive the system information message in parallel from a base station in a Narrowband Internet of Things (NB-IoT) downlink scheduling period, in which the HARQ processes respectively correspond to the HARQ buffer blocks.