N-bit Constant Adder Subtractor FPGA LUT Implementation
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Solution Overview
Problem
Existing N-bit constant coefficient adder/subtractor implementations in FPGAs face inefficiencies due to the need for arithmetic mode, extra logic, and carry chains, limiting area and delay optimization, and resulting in suboptimal LUT utilization and increased resource usage.
Innovation Solution
The proposed solution eliminates the need for arithmetic mode and carry chains by configuring LUTs in normal mode, allowing for post-mapping optimization and efficient interconnection of LUTs to implement N-bit constant adder/subtractors using a cascade chain approach, minimizing delay and optimizing area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If arithmetic mode is used to implement N-bit constant coefficient adder/subtractor, then the circuit can generate two functions from a single LUT, but post-mapping optimization algorithms cannot be applied and area/delay optimization is limited
Solution Approach 1:
The patent segments the adder/subtractor into N separate LUTs, each handling one bit of the addition/subtraction operation. This segmentation allows each LUT to operate in normal mode rather than arithmetic mode, enabling post-mapping optimization algorithms to be applied to each LUT independently while maintaining the overall functionality of the N-bit adder/subtractor.
2Productivity
If arithmetic mode with carry chain is used, then N-bit adder/subtractor can be implemented in N LUTs, but extra logic and dedicated carry chain are required increasing device complexity
Solution Approach 1:
The patent extracts and eliminates the dedicated carry chain from the architecture. Instead of using a separate carry chain to propagate carries between LUTs, the design uses the output of each LUT to directly feed into the next LUT through normal routing. This removes the need for special carry chain infrastructure while maintaining efficient carry propagation through the sequential LUT arrangement.
Solution Approach 2:
The patent makes the LUTs universal by configuring them in normal mode rather than arithmetic mode. Each LUT can be independently optimized and configured for its specific bit operation without being constrained by arithmetic mode requirements. This universality allows the same LUT structure to be used across all N bits without requiring special arithmetic mode handling or dedicated carry chain logic.
3Ease of manufacture
If normal mode LUTs are used without arithmetic mode, then post-mapping optimization can be applied, but the number of LUTs required increases to N+N/3
Solution Approach 1:
The patent employs a dynamic approach where each LUT is configured to perform addition or subtraction based on the constant coefficient values. By dynamically selecting the appropriate operation for each LUT based on the constant K, the design achieves optimal LUT utilization without requiring additional LUTs. This dynamic configuration allows N LUTs to handle N-bit operations efficiently while maintaining compatibility with post-mapping optimization algorithms.
4Device complexity
If N-bit adder/subtractor is implemented with ripple carry, then the circuit is simple to implement, but delay is directly proportional to N+1
Solution Approach 1:
The patent performs preliminary action by pre-configuring each LUT with the appropriate constant coefficient values and operation type before the actual addition/subtraction operation. This preliminary configuration allows the LUTs to be ready for immediate computation without requiring complex carry propagation logic, reducing the overall delay while maintaining simple circuit structure.
Data Source
AI summary
An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic for support of arithmetic mode and carry chains. For FPGAs supporting 4-input LUTs, the concept is further enhanced with the capability to perform addition and subtraction dynamically, by exploiting the fourth unused input of the LUTs. Another embodiment involves delay-optimized realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs with 4-input LUTs. LUTs in the implementation have single output generation capability without any carry generation and propagation. The implementation utilizes N+1 LUTs and gives a delay proportional to N/2 of routing resource used. However, the implementation becomes more efficient by the use of cascade chains. The delay optimization is achieved by doing computation in two parallel chains.