NBTI Controller Mitigates Memory Degradation

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Solution Overview

Problem

Bias temperature instability (BTI), particularly negative BTI (NBTI), causes performance degradation in semiconductor devices by introducing uneven electrical stress, leading to increased threshold voltage and reduced switching speed during low power mode or high temperature, high voltage testing.

Innovation Solution

A controller system that includes an NBTI controller with an oscillator and signal pattern generator, which generates regular clocking signals to mitigate NBTI by aligning command and address transition timings with clock signals, ensuring signal propagation and reducing DC stress in memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If memory device operates in low power mode or high temperature high voltage testing, then power consumption is reduced, but negative BTI degradation increases due to uneven electrical stress

Engineering Contradiction:
Improvepower consumptionVSAvoiddevice performance
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies periodic action by generating regular clocking signals to activate memory circuits at specific time intervals. The controller generates clock signals that periodically activate command and address circuits, ensuring periodic signal propagation through the memory device. This periodic activation prevents continuous DC stress while maintaining circuit functionality, thereby mitigating NBTI degradation during low power mode operation.

Inventive Principle:
Principle #19Periodic action

2Reliability

If high voltage testing is performed, then device reliability is improved, but uneven electrical stress causes increased NBTI degradation

Engineering Contradiction:
Improvedevice reliabilityVSAvoiduneven electrical stress
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent uses periodic clocking signals to activate memory circuits only during specific time intervals rather than continuously. This periodic activation ensures that high voltage stress is applied uniformly across all memory circuits over time, preventing the accumulation of uneven electrical stress that causes NBTI degradation while still achieving reliable device testing.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent maintains continuous useful action by ensuring that clocking signals periodically activate all memory circuits, command circuits, and address circuits. This continuous periodic activation ensures that all circuits experience electrical stress uniformly over time, preventing localized degradation while maintaining overall device functionality and reliability.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If transistor threshold voltage increases due to NBTI, then device reliability is improved, but switching speed decreases

Engineering Contradiction:
Improvedevice reliabilityVSAvoidswitching speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies periodic clocking signals to activate memory circuits at controlled intervals. This periodic activation prevents continuous DC stress that would cause threshold voltage drift, thereby maintaining stable transistor characteristics and consistent switching speed while still achieving reliable operation through regular circuit activation.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250104792A1Apparatus including BTI controller
Publication Date: 2025.03.27 MICRON TECHNOLOGY INC
  • US20250104792A1 patent drawing
  • US20250104792A1 patent drawing
  • US20250104792A1 patent drawing

AI summary

According to one or more embodiments of the disclosure, an apparatus comprises a memory device and a bias temperature instability (BTI) controller. The BTI controller generates and outputs a command and address signal for memory testing. The command and address signal causes the memory device in the idle state to operate for the testing.