NCEM Fill Cells Embedded in Standard Cell Logic Regions
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Solution Overview
Problem
Current semiconductor manufacturing processes lack efficient methods for in-line detection of defects and process parameter monitoring using non-contact electrical measurements (NCEM) within standard cell logic regions, particularly in fill cells, which are crucial for optimizing manufacturing yields and quality control.
Innovation Solution
The integration of NCEM-enabled fill cells with Design of Experiments (DOEs) within standard cell logic regions, utilizing test structures that allow for non-contact voltage contrast inspection and measurement, enabling the detection of defects and process anomalies through the use of charged particle beams and optimized beam scanning techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If test structures are embedded within standard cell logic regions, then manufacturing precision and defect detection capability are improved, but device complexity increases
Solution Approach 1:
The patent merges test structures with standard cell logic regions by integrating NCEM-enabled fill cells, tap cells, decap cells, and scribe lines directly into the standard cell area. This combination allows test structures to be embedded within the contiguous standard cell region, enabling defect detection without requiring separate dedicated test areas, thus improving manufacturing precision while managing device complexity through unified design
Solution Approach 2:
The patent implements multi-functional cells that serve both standard logic functions and test functions. Fill cells, tap cells, and decap cells are designed to perform their primary functions while simultaneously enabling non-contact electrical measurements for defect detection. This universality allows the same structures to serve multiple purposes, improving defect detection capability without proportionally increasing device complexity
2Measurement precision
If non-contact electrical measurements are implemented using charged particle beams, then measurement precision is improved, but productivity decreases due to extended inspection time
Solution Approach 1:
The patent performs non-contact electrical measurements at multiple intermediate stages during the semiconductor manufacturing process, before final chip completion. By conducting inspections earlier in the process flow using NCEM on wafers and intermediate structures, the system detects defects when they first occur, enabling early intervention and reducing the need for rework or disposal of finished products, thus maintaining productivity while improving measurement precision
Solution Approach 2:
The patent implements continuous non-contact electrical measurement capabilities throughout the manufacturing process by integrating NCEM-enabled structures that can be inspected at various stages. The charged particle beam inspection system continuously monitors test structures during process steps, providing ongoing defect detection without interrupting the manufacturing flow, thereby maintaining both measurement precision and productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise and efficient detection of defects and process anomalies, improving manufacturing yields and quality control by providing real-time data on semiconductor wafer and chip production, thereby enhancing the reliability and efficiency of the semiconductor manufacturing process.
Implementation Method 1
non-contact voltage contrast inspection and measurement, enabling the detection of defects and process anomalies through the use of charged particle beams
Data Source
AI summary
An IC includes a contiguous standard cell area with first, second, and third TS-GATE-short-configured test area geometries disposed therein. In some embodiments, the contiguous standard cell area may further include: fourth and fifth TS-GATE-short-configured test area geometries, and/or other test area geometries, such as tip-to-tip-short, tip-to-side-short, diagonal-short, corner-short, interlayer-overlap-short, via-chamfer-short, merged-via-short, snake-open, stitch-open, via-open, or metal-island-open.