NCF Retention Structures for Stacked Semiconductor Assemblies

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Solution Overview

Problem

During the assembly of semiconductor device assemblies with non-conductive film (NCF), the NCF can unpredictably squeeze out from the sides of the device stack when heated and compressed, leading to increased size, potential voids, and prevention of mold material from reaching the sides.

Innovation Solution

Incorporating retention structures on the bottom surface of each stacked device, which are designed to constrain and redirect the flow of NCF, ensuring it fills the desired regions and minimizing squeeze-out to areas where it won't negatively impact the assembly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If non-conductive film is applied to fill gaps between stacked devices, then protection and structural integrity are improved, but the film unpredictably squeezes out during heating and compression

Engineering Contradiction:
Improveprotection of stacked devicesVSAvoidposition control of non-conductive film
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Retention structures are formed on the bottom surface of each stacked device before the non-conductive film is applied. These pre-formed structures create designated pathways that guide the film during subsequent heating and compression, preventing unpredictable squeeze-out while maintaining protection benefits

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The retention structures act as intermediary elements between the stacked devices and the non-conductive film. They mediate the interaction by providing controlled pathways for the film, allowing it to fill gaps effectively while preventing harmful squeeze-out during the bonding process

Inventive Principle:
Principle #24Intermediary (Mediator)

2Volume of stationary object

If non-conductive film is compressed during assembly, then gap filling and protection are improved, but squeeze-out increases device size and creates voids

Engineering Contradiction:
Improvegap filling between devicesVSAvoiddevice stack dimensions
Core Design Contradiction:
Volume of stationary objectVSShape

Solution Approach 1:

The retention structures segment the bottom surface of each stacked device into distinct regions. This segmentation creates controlled zones that direct the non-conductive film into specific pathways, ensuring gap filling occurs in designated areas while preventing spread to regions that would increase overall device size or create voids

Inventive Principle:
Principle #1Segmentation

3Strength

If non-conductive film is heated and compressed, then bonding and structural integrity are improved, but mold material cannot reach the sides of the device

Engineering Contradiction:
Improvebonding of stacked devicesVSAvoidcoverage of mold material
Core Design Contradiction:
StrengthVSArea of stationary object

Solution Approach 1:

The retention structures create local variations in the bottom surface geometry, providing different functions in different regions. The structures are positioned and sized to allow non-conductive film to be retained in critical bonding areas while leaving peripheral regions open for mold material access, thus achieving both strong bonding and complete mold coverage

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250062269A1Semiconductor devices with non-conductive film retention arrangements, and associated assemblies and methods
Publication Date: 2025.02.20 MICRON TECHNOLOGY INC
  • US20250062269A1 patent drawing
  • US20250062269A1 patent drawing
  • US20250062269A1 patent drawing

AI summary

A semiconductor device assembly is provided, which comprises a vertical stack of semiconductor devices, the vertical stack including a plurality of electrical interconnects, a plurality of retention structures, and a non-conductive film (NCF) between each adjacent pair of semiconductor devices of the vertical stack. The plurality of retention structures between each adjacent pair of semiconductor devices is disposed peripherally to the corresponding plurality of electrical interconnects. Each of the plurality of retention structures has a height less than a space between the corresponding adjacent pair of semiconductor devices, and the plurality of retention structures between each adjacent pair of semiconductor devices has a smaller first average pitch between adjacent ones of the plurality of retention structures than a second average pitch between adjacent ones of the corresponding plurality of electrical interconnects.