NCFET Complementary Capacitance Matching Stacked Nanosheets
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in achieving reduced footprint and improved performance for negative capacitance field effect transistors (NCFETs) due to limitations in subthreshold swing and capacitance matching, particularly in non-planar transistor architectures like nanosheet FETs.
Innovation Solution
The method involves forming a negative capacitance field effect transistor (NCFET) device with stacked n-type and p-type nanosheets, incorporating a dielectric interfacial layer with metal-induced oxygen vacancies, and a shared internal gate configuration to achieve complementary capacitance matching and steep switching, thereby reducing the device footprint and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If stacked nanosheet structures are used to reduce device footprint, then area is reduced, but achieving complementary capacitance matching becomes more difficult
Solution Approach 1:
The patent transitions from planar to three-dimensional stacked nanosheet architecture, stacking multiple n-type and p-type nanosheets vertically to achieve complementary capacitance matching. This vertical stacking enables compact footprint while maintaining the necessary capacitance balance through controlled layer configurations.
Solution Approach 2:
The patent applies different work function metal layers (pWF and nWF) to specific regions of the stacked nanosheets to achieve type-specific electrical characteristics. By locally tailoring the metal layer properties in different stack regions, complementary capacitance matching is achieved despite the compact stacked geometry.
2Reliability
If ferroelectric layer is added to achieve negative capacitance effect, then subthreshold swing is improved, but device complexity increases
Solution Approach 1:
The patent employs a composite gate stack structure integrating ferroelectric material with high-k dielectric layers and work function metals. This composite approach achieves the negative capacitance effect for improved subthreshold swing while the systematic layering maintains fabrication compatibility and manages structural complexity.
Solution Approach 2:
The gate stack is designed to perform multiple functions simultaneously: the ferroelectric layer provides negative capacitance, the high-k dielectric ensures proper electrical isolation and field control, and the work function metals establish appropriate threshold voltages. This multi-functional integration achieves performance improvement without proportionally increasing complexity.
3Reliability
If multiple metal layers are used for work function tuning, then electrical performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent systematically varies the thickness, composition, and stacking sequence of metal layers to tune work function values for specific n-type and p-type nanosheet configurations. By controlling these parameters during fabrication, the desired electrical characteristics are achieved while managing the precision requirements through established deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved subthreshold swing and capacitance matching, allowing for a smaller footprint and increased performance without the typical layout area penalties, by utilizing a dielectric interfacial layer with metal-induced oxygen vacancies and a shared internal gate configuration in NCFETs.
Implementation Method 1
the dielectric interfacial layer including metal induced oxygen vacancies
Implementation Method 2
An NCFET includes a ferroelectric (FE) layer within the gate stack of a transistor, which acts under certain conditions as a negative capacitance to overcome the fundamental limit of sub-threshold swing (SS) in transistors
Data Source
AI summary
A negative capacitance field effect transistor (NCFET) device is provided. The NCFET device includes a substrate, and a transistor stack structure formed on the substrate. The nanosheet stack structure includes a PFET region and an NFET region, the PFET region including a pWF metal layer stack and the NFET region including a nWF metal layer stack. The NCFET device also includes a dielectric interfacial layer formed on the transistor stack structure, the dielectric interfacial layer including metal induced oxygen vacancies, and the dielectric interfacial layer formed on a portion of the transistor stack structure. The NCFET device also includes a top electrode formed on the dielectric interfacial layer.