Negative Capacitance FET Header Switches for Low Power
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Solution Overview
Problem
Current semiconductor devices face challenges in minimizing power consumption while maintaining high-speed operations, as existing technologies often require larger chip areas due to additional circuitry for power control, and there is a trade-off between power consumption and chip area, especially with higher threshold voltage devices leading to increased on-resistance.
Innovation Solution
The use of negative capacitance field effect transistors (NC FETs) as header and/or footer switches, which incorporate a ferroelectric capacitor connected in series with the gate of a MOS FET, allowing for voltage amplification and reduced off-leakage current without increasing the threshold voltage of the MOS FET portion, thereby reducing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional MOS FETs with higher threshold voltage are used to reduce power consumption, then power consumption decreases, but on-resistance increases
Solution Approach 1:
The patent changes the electrical parameters of the FET by introducing a negative capacitance element that modifies the gate voltage characteristics. This allows the device to operate with effective threshold voltage modulation without permanently increasing the physical threshold voltage, thereby maintaining low on-resistance while achieving power savings through dynamic voltage control
Solution Approach 2:
The negative capacitance element acts as an intermediary between the control voltage and the channel, providing voltage amplification. This mediator enables the system to achieve higher effective gate voltages (and thus lower on-resistance) with smaller control voltages, resolving the trade-off between power consumption and on-resistance
2Use of energy by moving object
If additional circuitry for power control is added to minimize power consumption, then power consumption decreases, but chip area increases
Solution Approach 1:
The patent merges the power control function directly into the FET structure by integrating the negative capacitance element with the gate. This combination eliminates the need for separate power control circuitry, achieving power management without increasing chip area
Solution Approach 2:
The negative capacitance FET structure serves multiple functions simultaneously: it provides the primary switching function, implements power control, and enables voltage amplification. This multi-functionality reduces the need for additional dedicated power control circuitry, thereby minimizing chip area while managing power consumption
3Loss of energy
If threshold voltage of MOS FET is increased to reduce leakage current, then standby leakage current decreases, but on-resistance increases
Solution Approach 1:
The patent introduces dynamic voltage control through the negative capacitance element, allowing the effective threshold voltage to be adjusted in real-time. This dynamic adjustment enables the system to maintain high threshold voltage characteristics during standby (reducing leakage) while achieving low on-resistance during active operation through voltage amplification
Solution Approach 2:
The negative capacitance element dynamically changes the electrical parameters of the FET by providing voltage amplification. This allows the system to effectively modulate the threshold voltage without permanently increasing it, thereby reducing standby leakage current while maintaining low on-resistance when needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
NC FETs achieve lower standby leakage current, lower on-resistance, and smaller device area compared to traditional MOS FETs, enabling enhanced operational speed and reduced chip area, with a 63% and 55% reduction in device area for LVT and SVT MOS FETs respectively, and a significant decrease in standby leakage current.
Implementation Method 1
a negative capacitor showing a negative capacitance and having a first terminal and a second terminal, and the first terminal is electrically coupled to a gate of the MOS FET
Implementation Method 2
the capacitor dielectric layer is a ferroelectric material including one or more selected from the group consisting of ZrO2, ZrAlSiO, HfO2, HfZrO2, HfO2 doped with Zr (HfZrOx), HfO2 doped with Al (HfAlOx), and HfO2 doped with Si (HfSiOx)
Data Source
AI summary
A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.