NCFET Memory Device With Ferroelectric Layer for On-Current
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Solution Overview
Problem
Existing memory technologies face challenges in achieving high on-current at lower gate voltages, which limits their performance and efficiency.
Innovation Solution
The implementation of a negative capacitance field effect transistor (NCFET) with a ferroelectric layer between the gate electrode and the gate dielectric layer, which generates a negative capacitance effect, allowing for increased on-current at the same or lower gate voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional memory technologies are used, then device structure is simple, but on-current is insufficient at lower gate voltages
Solution Approach 1:
The patent implements a nested structure where the ferroelectric layer is embedded between the gate electrode and the gate dielectric layer. This nested configuration allows the ferroelectric material to be integrated within the existing transistor structure, achieving high on-current through the negative capacitance effect while maintaining compatibility with conventional manufacturing processes and avoiding excessive structural complexity.
2Power
If gate voltage is increased to achieve higher on-current, then on-current increases, but power consumption increases
Solution Approach 1:
The patent changes the electrical parameters of the gate structure by introducing the ferroelectric layer with negative capacitance. This parameter change allows the transistor to achieve higher on-current at the same or lower gate voltage, thereby reducing power consumption while maintaining or improving current drive capability.
Solution Approach 2:
The ferroelectric layer acts as an intermediary between the gate electrode and the channel, mediating the electric field distribution. This intermediary structure enhances the gate's control over the channel, enabling higher on-current at lower gate voltages and thus reducing power consumption.
3Power
If ferroelectric layer is added to achieve negative capacitance effect, then on-current increases, but manufacturing complexity increases
Solution Approach 1:
By nesting the ferroelectric layer within the existing gate structure, the patent integrates the complex functionality into a familiar manufacturing framework. The ferroelectric layer is deposited between the gate electrode and gate dielectric layer using standard semiconductor fabrication techniques, thereby achieving high on-current while minimizing disruptions to existing manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The NCFET achieves a significant increase in on-current by a factor of 2 to 10 under the same gate voltage, reducing power consumption and enhancing memory performance.
Implementation Method 1
The implementation of a negative capacitance field effect transistor (NCFET) with a ferroelectric layer between the gate electrode and the gate dielectric layer, which generates a negative capacitance effect, allowing for increased on-current at the same or lower gate voltage.
Data Source
AI summary
A memory device and a manufacturing method are provided. The memory device includes a substrate, a transistor, and a memory cell. The substrate has a semiconductor device and a dielectric structure disposed on the semiconductor device. The transistor is disposed over the dielectric structure and is electrically coupled with the semiconductor device. The semiconductor device includes a gate, a channel layer, source drain regions, and a stack of a gate dielectric layer and a first ferroelectric layer. The gate and the source and drain regions are disposed over the dielectric structure. The channel layer is located between the source and drain regions. The stack of the gate dielectric layer and the first ferroelectric layer is disposed between the gate and the channel layer. The memory cell is disposed over the transistor and is electrically connected to one of the source and drain regions. The memory cell includes a ferromagnetic layer or a second ferroelectric layer.