Bootstrap Inverter Circuit for True 0V and VDD Logic Levels
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Solution Overview
Problem
Conventional inverters using N-channel transistors face issues where the output voltage does not reach complete 0V when logic '0' and is less than VDD when logic '1', due to resistance ratios of transistors determining output voltage.
Innovation Solution
An inverter circuit is designed with a first and second load transistor, a driving transistor, and a control transistor, along with a capacitor in the bootstrap inverter, ensuring the output voltage reaches 0V when logic '0' and VDD when logic '1' by controlling transistor states and using a bootstrap mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an N-channel inverter uses a load transistor and driving transistor with specific resistance ratios to achieve complete 0V output, then the output voltage reaches 0V for logic '0', but the output voltage becomes less than VDD for logic '1'
Solution Approach 1:
The patent introduces a control transistor as an intermediary element to manage the output voltage. This control transistor works in conjunction with the load transistor and driving transistor to precisely regulate the output voltage, enabling it to reach complete 0V for logic '0' while maintaining proper voltage levels for logic '1' through coordinated transistor operation.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the operating states of multiple transistors (load transistor, driving transistor, and control transistor) to achieve different output voltage levels. By changing the resistance ratios and conduction states of these transistors, the circuit can precisely control the output voltage to reach 0V when needed while maintaining VDD levels at other times.
2Manufacturing precision
If the resistance ratio of transistors is adjusted to achieve complete 0V output, then the output voltage reaches 0V for logic '0_', but the output current becomes small when output is VDD
Solution Approach 1:
The control transistor serves as an intermediary that decouples the relationship between resistance ratio and output current. By introducing this additional control element, the circuit can achieve complete 0V output through precise transistor gating while maintaining adequate output current capability through the coordinated action of all three transistors, eliminating the direct trade-off present in two-transistor configurations.
3Reliability
If a CMOS inverter is used to achieve proper output voltage levels, then the output voltage reaches VDD for logic '1' and 0V for logic '0_', but the circuit complexity increases due to requiring both P-channel and N-channel transistors
Solution Approach 1:
The patent achieves CMOS-like output voltage levels (VDD and 0V) by dynamically changing the parameters and conduction states of N-channel transistors in a multi-transistor configuration. Through precise control of the load transistor, driving transistor, and control transistor, the circuit replicates the voltage level characteristics of CMOS inverters while using only N-channel devices, thus achieving reliable output levels with a specific transistor configuration approach.
Data Source
AI summary
The present invention provides an inverter and a bootstrap inverter with improved output characteristics. The inverter comprises a first and second load transistors, a driving transistor, and a control transistor. The control transistor, when turned on, effectively grounds the source of the first load transistor, ensuring a 0V output. The bootstrap inverter further includes a bootstrap transistor and a capacitor. This configuration solves the problems of output voltage being lower than VDD for logic ‘1’ and not completely 0V for logic ‘0’, achieving ideal output levels.