N-channel Transistor Stress Liner Uniformity via Buffer Layer
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Solution Overview
Problem
Conventional techniques for forming stressed dielectric layers in highly scaled semiconductor devices suffer from reduced efficiency due to limited conformal deposition capabilities, leading to process non-uniformities and defects such as voids and etch non-uniformities, which affect transistor performance and strain induction.
Innovation Solution
An enhanced stress liner approach is implemented, where a third dielectric layer with a lower internal stress level is formed above previously patterned stress-inducing layers to reduce non-uniformities and enhance strain induction in N-channel transistors, using a dual stress liner sequence with an additional dielectric material acting as a buffer layer to improve deposition uniformity and etch controllability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual stress liner approach is used to induce strain in channel regions, then transistor performance is enhanced, but patterning-induced non-uniformities and defects such as voids occur due to limited conformal deposition capabilities in highly scaled devices
Solution Approach 1:
The patent divides the stress-inducing layer into two separate layers: a first stress-inducing layer deposited conformally to induce strain in the channel region, and a second stress-inducing layer deposited to provide additional stress while maintaining uniformity. This segmentation allows each layer to fulfill its specific function without the defects that arise when attempting to deposit a single thick layer with high stress in highly scaled devices.
2Speed
If the channel length is reduced to increase operating speed, then the drive current capability increases, but short channel effects occur that reduce controllability of channel conductivity
Solution Approach 1:
The patent modifies the physical parameters of the channel region by inducing mechanical strain through stress-inducing dielectric layers. This strain alters the mobility of charge carriers in the channel, effectively changing the electrical characteristics without requiring further reduction of channel length, thus maintaining controllability while improving speed.
3Reliability
If tensile strain is created in the channel region to increase electron mobility, then N-channel transistor performance is enhanced, but the deposition process becomes more complex
Solution Approach 1:
The patent applies stress-inducing layers with specific stress characteristics (tensile or compressive) selectively over different transistor types (N-channel or P-channel). The first stress-inducing layer is configured to provide tensile strain over N-channel transistors to enhance electron mobility, while the second layer provides complementary stress. This local differentiation of stress properties enhances N-channel performance without requiring complex deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances the performance of N-channel transistors by reducing patterning-induced non-uniformities and improving strain-inducing mechanisms, while maintaining the performance of P-channel transistors, resulting in increased operating speed and reliability of logic CMOS devices.
Implementation Method 1
forming a first stress-inducing layer above a first transistor formed above a substrate, wherein the first stress-inducing layer generates a first type of stress
Implementation Method 2
forming a second stress-inducing layer above a second transistor, wherein the second stress-inducing layer generates a second type of stress
Data Source
AI summary
By forming an additional dielectric material, such as silicon nitride, after patterning dielectric liners of different intrinsic stress, a significant increase of performance of N-channel transistors may be obtained while substantially not contributing to a performance loss of the P-channel transistor.