NCMOS Logic Circuit Topology for Noise Margin in Flexible Electronics
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Solution Overview
Problem
The challenge in flexible electronics is the lack of robust CMOS capability, with NMOS being state-of-the-art, leading to limitations in performance mismatch, complex design, and reduced integration due to the difficulty in combining complementary materials like CMOS and NMOS into a single manufacturable process.
Innovation Solution
The development of NCMOS technology, which uses NMOS devices to create a quasi-CMOS design, allowing for existing NMOS processing and achieving fan-out and noise margin comparable to CMOS, enabling the use of existing design tools and libraries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If NMOS logic is used in flexible electronics, then manufacturing is simplified and state-of-the-art performance is achieved, but power efficiency deteriorates and noise margin is reduced compared to CMOS
Solution Approach 1:
The circuit is segmented into two distinct paths: an NMOS pull-down network for logic functionality and a separate PMOS pull-up network for power efficiency. This segmentation allows each transistor type to operate in its optimal regime while working together in the same circuit, resolving the contradiction between manufacturing simplicity and power efficiency.
Solution Approach 2:
The invention creates a composite logic structure combining NMOS and PMOS transistors in a single gate. This composite approach leverages the advantages of both transistor types - the manufacturing ease and high-speed performance of NMOS plus the low leakage and power efficiency of PMOS - thereby resolving the contradiction between ease of manufacture and power efficiency.
2Ease of manufacture
If NMOS logic is used in flexible electronics, then manufacturing is simplified, but noise margin deteriorates compared to CMOS
Solution Approach 1:
The circuit is segmented into two distinct paths: an NMOS pull-down network for logic functionality and a separate PMOS pull-up network for power efficiency. This segmentation allows each transistor type to operate in its optimal regime while working together in the same circuit, resolving the contradiction between manufacturing simplicity and power efficiency.
Solution Approach 2:
The invention creates a composite logic structure combining NMOS and PMOS transistors in a single gate. This composite approach leverages the advantages of both transistor types - the manufacturing ease and high-speed performance of NMOS plus the low leakage and power efficiency of PMOS - thereby resolving the contradiction between ease of manufacture and power efficiency.
3Reliability
If complementary materials (PMOS and NMOS) are combined into a single manufacturable process, then CMOS performance is achieved, but manufacturing complexity increases significantly
Solution Approach 1:
The circuit is segmented into two distinct paths: an NMOS pull-down network for logic functionality and a separate PMOS pull-up network for power efficiency. This segmentation allows each transistor type to operate in its optimal regime while working together in the same circuit, resolving the contradiction between manufacturing simplicity and power efficiency.
Solution Approach 2:
The invention creates a composite logic structure combining NMOS and PMOS transistors in a single gate. This composite approach leverages the advantages of both transistor types - the manufacturing ease and high-speed performance of NMOS plus the low leakage and power efficiency of PMOS - thereby resolving the contradiction between ease of manufacture and power efficiency.
4Area of stationary object
If channel length is reduced to minimize footprint, then area is reduced, but noise margin deteriorates
Solution Approach 1:
The circuit is segmented into two distinct paths: an NMOS pull-down network for logic functionality and a separate PMOS pull-up network for power efficiency. This segmentation allows each transistor type to operate in its optimal regime while working together in the same circuit, resolving the contradiction between manufacturing simplicity and power efficiency.
Solution Approach 2:
The invention creates a composite logic structure combining NMOS and PMOS transistors in a single gate. This composite approach leverages the advantages of both transistor types - the manufacturing ease and high-speed performance of NMOS plus the low leakage and power efficiency of PMOS - thereby resolving the contradiction between ease of manufacture and power efficiency.
Data Source
Figure 1a~1b
Figure 2a
Figure 2b
AI summary
An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.