Numerically Controlled Oscillator With Low-Power Edge Switching
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Solution Overview
Problem
Numerically-controlled oscillators (NCOs) with higher-frequency input clocks achieve more accurate output frequencies with less jitter but consume more power, and existing methods struggle to generate precise output frequencies while minimizing power consumption.
Innovation Solution
A method and apparatus that utilize a control circuit running at a lower frequency than the input clock to generate an output clock signal by toggling based on either a first or second number of input clock edges, allowing for programmable frequency division and reducing power consumption by using a clock generator circuit with a linear feedback shift register counter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a higher-frequency input clock is used in the NCO, then output frequency accuracy is improved and jitter is reduced, but power consumption increases
Solution Approach 1:
The patent segments the high-frequency clock operation into two distinct circuits: a control circuit that runs at lower frequency to generate control information, and a clock generator circuit that runs at high frequency to generate the output clock. This segmentation allows the power-intensive high-frequency operation to be minimized only where absolutely necessary for frequency accuracy, while the control functions operate at lower power consumption.
Solution Approach 2:
The patent introduces control information as an intermediary between the low-frequency control circuit and the high-frequency clock generator. This control information (including start signal, stop signal, and overflow signal) mediates the interaction between the two circuits, allowing the high-frequency clock to be activated only when needed for precise frequency generation, thereby reducing overall power consumption while maintaining accuracy.
2Measurement precision
If a higher-frequency input clock is used in the NCO, then output frequency accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the NCO into two functionally distinct segments: a control circuit responsible for generating control information based on desired output frequency, and a clock generator circuit responsible for producing the actual output clock signal. This segmentation allows each circuit to be optimized independently, reducing overall complexity compared to a single unified high-frequency NCO circuit.
Solution Approach 2:
The control information serves as an intermediary that bridges the simple low-frequency control circuit and the high-frequency clock generator. By using this intermediary signal mechanism, the patent avoids the complexity of implementing complex control logic within a single high-frequency circuit, thereby reducing overall device complexity while maintaining frequency accuracy.
Data Source
AI summary
Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.