Free-Running NCO Phase Alignment Across Data Rate Changes
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Solution Overview
Problem
Numerically controlled oscillators face challenges in dynamically changing data rates without aligning the phase of new signals with previous signals, leading to issues with downstream components or requiring time-consuming system restarts.
Innovation Solution
A reconfigurable numerically controlled oscillator system that uses a free-running counter to maintain a consistent phase reference by continuing to count without being reset, allowing the phase accumulator to receive a new phase value and map it to a periodic signal, ensuring phase alignment across data rate changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the data rate of the numerically controlled oscillator is dynamically changed to match upstream or downstream digital signal processing circuits, then the adaptability of the system is improved, but the phase alignment between previous and new signals deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing phase offset values in a lookup table before data rate changes occur. When a data rate change is detected, the corresponding phase offset is immediately retrieved and applied to the phase accumulator, eliminating phase misalignment without requiring system restart. This advance preparation resolves the contradiction by maintaining phase alignment (reliability) while enabling dynamic data rate changes (adaptability).
2Reliability
If the system is restarted to realign phase after data rate changes, then phase alignment is restored, but the loss of time increases
Solution Approach 1:
The patent pre-calculates phase offset values for all possible data rate transitions and stores them in a lookup table. When a data rate change occurs, the appropriate phase offset is immediately retrieved and applied to the phase accumulator, restoring phase alignment in a single clock cycle without system restart. This eliminates the time loss associated with restarts while maintaining phase alignment reliability.
Solution Approach 2:
The patent replaces the mechanical system approach (physical system restart) with an electronic/software-based solution (phase offset calculation and application). Instead of restarting the entire system to realign phases, the invention uses digital signal processing techniques to calculate and apply phase corrections, dramatically reducing the time required to restore phase alignment while maintaining reliability.
3Reliability
If a free-running counter is used to maintain phase reference during data rate switching, then phase consistency is improved, but the device complexity increases
Solution Approach 1:
The patent implements a universal free-running counter that continuously counts clock cycles regardless of data rate changes, serving multiple functions: tracking elapsed time, calculating phase offsets for any data rate transition, and maintaining phase reference. This single multi-functional component maintains phase consistency across all operating conditions without requiring separate circuitry for each function, thereby limiting the increase in device complexity while achieving reliable phase consistency.
Solution Approach 2:
The patent introduces a phase-to-signal mapping circuit as an intermediary between the free-running counter and the output signal generation. This mapping circuit translates the continuous counter values into appropriate phase corrections based on the current data rate, acting as a mediator that reconciles the continuous counting with the discrete data rate changes. This intermediary approach maintains phase consistency while keeping the overall device complexity manageable through modular design.
Data Source
AI summary
A numerically controlled oscillator system for maintaining a consistent phase reference while switching data rates may include a numerically controlled oscillator (NCO) circuit. The NCO circuit may include a phase accumulator, a phase-to-signal mapping circuit, and a first free-running counter. The phase accumulator may receive a new phase value as an input in response to an update signal. The phase-to-signal mapping circuit may map a value from the phase accumulator to a periodic signal. The first free-running counter may continue counting, without being reset, while the numerically controlled oscillator system is switching digital data rates. The first free-running counter may be configured to provide the new phase value to the phase accumulator using a representation of a counter value of the first free-running counter and a frequency tuning word defined by a representation of a frequency of the periodic signal.