NCO Clock Phase Smoothing for Low-Jitter Output Timing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Numerically-controlled oscillators (NCOs) suffer from jitter due to time discretization of clock phase, resulting in variable time between clock edges, despite precise average frequency control.

Innovation Solution

A phase smoothing system is introduced, comprising a numerically-controlled oscillator (NCO) with a phase error calculation module and a clock phase selectable delay, which adjusts the phase of each NCO clock pulse to minimize jitter by compensating for phase errors, allowing output clock edges to approximate ideal phase without aligning with input clock edges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If NCO clock edges are aligned to input clock edges for simple implementation, then device complexity is reduced, but jitter increases to one input clock period

Engineering Contradiction:
ImproveNCO implementation complexityVSAvoidclock jitter
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

A phase error calculation module is introduced as an intermediary component that computes the phase difference between ideal and actual NCO clock edges. This module processes the phase error information and feeds it to a delay control mechanism, which then adjusts the NCO clock phase accordingly. This intermediary processing stage resolves the contradiction by enabling precise phase control without requiring complete redesign of the NCO architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements a feedback mechanism where the phase error calculation module continuously monitors the phase difference between ideal and actual clock edges, and this error information is used to adjust the NCO clock phase in real-time. The feedback loop reduces jitter by dynamically compensating for phase deviations while maintaining implementation feasibility through standardized digital signal processing techniques.

Inventive Principle:
Principle #23Feedback

2Reliability

If NCO clock phase is adjusted to reduce jitter, then clock stability is improved, but device complexity increases due to additional modules

Engineering Contradiction:
Improveclock stabilityVSAvoidphase smoothing system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system changes the phase parameter of the NCO clock dynamically based on calculated phase errors. By adjusting the phase parameter in response to measured deviations, the system achieves improved clock stability. The parameter changes are implemented through digital control mechanisms that modify clock edge timing without requiring fundamental architectural changes, thus limiting the increase in device complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The phase smoothing function is segmented into distinct modular components: a phase error calculation module that computes phase differences, and a delay control module that applies corrections. This segmentation allows each module to perform a specific function efficiently, reducing overall system complexity compared to a monolithic design. The modular approach enables independent optimization and simplifies implementation of the phase adjustment mechanism.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7826582B2Numerically controlled oscillator (NCO) output clock phase smoothing
Publication Date: 2010.11.02 NAT SEMICON CORP
  • US7826582B2 patent drawing
  • US7826582B2 patent drawing
  • US7826582B2 patent drawing

AI summary

A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency that are phase-adjusted to more closely match an ideal output clock phase. Edges of the output clock need not necessarily align to the edges of the input clock.