Hardware NCU for Global TLB Demap Across Multiprocessor Cores
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Solution Overview
Problem
Current systems face significant overhead in processing software interrupts for demapping obsolete virtual to physical address translations across multiple cores and processors, leading to decreased performance, especially in systems with increasing numbers of cores and frequent changes to virtual memory.
Innovation Solution
A hardware-based method for invalidating obsolete translations using a non-cacheable unit (NCU) that issues and synchronizes global TLB demap operations across all affected cores and processors, reducing the need for software interrupts and minimizing system overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software interrupts are used to manage TLB demap operations across multiple cores and processors, then comprehensive address translation invalidation is achieved, but system overhead increases significantly and performance decreases
Solution Approach 1:
The patent replaces the software-based interrupt mechanism with a hardware-based TLB invalidation system. The TLB invalidation engine directly manages TLB entries across multiple cores through hardware mechanisms, eliminating the need for software interrupts and significantly reducing system overhead while maintaining reliable address translation validity.
Solution Approach 2:
The patent introduces a TLB invalidation engine as an intermediary component between the memory management unit and TLBs across multiple cores. This engine coordinates invalidation operations centrally, allowing comprehensive TLB management without requiring each core to process individual software interrupts.
2Productivity
If the number of processor cores increases, then computational capability improves, but the overhead for processing software interrupts for demap operations increases
Solution Approach 1:
The patent merges the TLB invalidation functionality into a centralized hardware engine that operates across all cores simultaneously. Instead of each core independently processing software interrupts, the invalidation engine consolidates the management of TLB entries system-wide, reducing per-core complexity while supporting increased core counts.
Solution Approach 2:
The patent substitutes software-based interrupt processing with a hardware-driven invalidation mechanism that automatically manages TLB entries across all cores. This hardware mechanism scales more efficiently with the number of cores, as it uses parallel hardware operations rather than sequential software interrupt handling.
3Adaptability or versatility
If frequent changes to virtual memory space occur, then system adaptability improves, but the overhead for processing demap operations increases
Solution Approach 1:
The patent replaces slow software-based demap operations with a hardware-accelerated TLB invalidation engine that can rapidly invalidate TLB entries across all cores. This hardware mechanism significantly reduces the time required for demap operations, enabling frequent virtual memory changes without substantial performance penalty.
Solution Approach 2:
The patent implements continuous TLB invalidation capability through the hardware engine, which can operate asynchronously and continuously to manage memory changes. This allows the system to maintain adaptability to frequent virtual memory modifications while minimizing the time loss associated with demap operations through efficient hardware handling.
Data Source
AI summary
A system and method for invalidating obsolete virtual/real address to physical address translations may employ translation lookaside buffers to cache translations. TLB entries may be invalidated in response to changes in the virtual memory space, and thus may need to be demapped. A non-cacheable unit (NCU) residing on a processor may be configured to receive and manage a global TLB demap request from a thread executing on a core residing on the processor. The NCU may send the request to local cores and/or to NCUs of external processors in a multiprocessor system using a hardware instruction to broadcast to all cores and/or processors or to multicast to designated cores and/or processors. The NCU may track completion of the demap operation across the cores and/or processors using one or more counters, and may send an acknowledgement to the initiator of the demap request when the global demap request has been satisfied.