N-Dimensional Word-Addressable Memory for Single-Cycle Bit Access
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Solution Overview
Problem
Conventional memory architectures are limited to one-dimensional data word addressing, requiring multiple access cycles for operations involving multiple bits, which is inefficient for high-performance applications that use data stored in bit patterns beyond conventional word arrangements.
Innovation Solution
An N-dimension addressable memory architecture with an N-dimension array of bit cells and logic for N-orthogonal addressing, allowing simultaneous access to multiple bits in a single memory cycle through N-dimensional addressing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional one-dimensional memory addressing is used, then the memory architecture is simple, but multiple memory access cycles are required for operations involving multiple bits
Solution Approach 1:
The patent transitions from conventional one-dimensional memory addressing to multi-dimensional addressing (e.g., two-dimensional array with row and column addresses). This dimensional expansion allows simultaneous access to multiple bits through array operations, reducing the number of memory access cycles required for operations involving multiple bits while maintaining manageable architectural complexity through systematic addressing schemes.
2Ease of operation
If conventional memory architectures are used, then the device complexity is low, but additional operations (shifting, masking) are required to manipulate bits
Solution Approach 1:
By organizing memory bits in multi-dimensional arrays and providing orthogonal addressing capabilities, the patent enables direct manipulation of bit patterns through array operations. This eliminates the need for additional shifting and masking operations, as bits can be accessed and manipulated directly in their natural array positions, simplifying the operational complexity.
Solution Approach 2:
The multi-dimensional memory architecture provides universal access capabilities that can handle various bit manipulation operations (reading, writing, shifting, masking) through a unified array operation interface. This multi-functional approach consolidates multiple operation types into a single coherent addressing and access mechanism.
3Productivity
If single ported memory is used, then the manufacturing is simple, but four memory access cycles are required to read/write specific bits
Solution Approach 1:
The patent employs multi-dimensional addressing where bits are organized in arrays with multiple address dimensions (e.g., row and column). This allows specific bits to be accessed efficiently by providing addresses in multiple dimensions simultaneously, reducing the number of sequential access cycles required compared to conventional single-dimensional addressing, while maintaining a relatively simple port structure.
Data Source
AI summary
An N-dimension addressable memory. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.