N-Type Dopant Gradient Source/Drain Junctions
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits leads to deep source/drain junctions and implantation damage, which can result in short-channel effects and transient-enhanced diffusion, making it challenging to achieve shallow junctions and low power dissipation.
Innovation Solution
A method involving the formation of a silicon-containing layer with a gradient dopant profile, followed by a rapid thermal annealing process at a lower temperature, which drives N-type dopants into the source/drain regions without ion implantation damage, and the use of a diffusion barrier to prevent over-diffusion of dopants, thereby reducing source/drain resistances and achieving shallow junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ion implantation methods are used to form source/drain regions, then doping can be achieved, but implantation damage and deep junctions occur leading to short-channel effects
Solution Approach 1:
The patent replaces the mechanical ion implantation process with a chemical diffusion process. Instead of physically implanting ions into the substrate (mechanical approach), dopants are introduced through chemical vapor deposition or liquid source diffusion, allowing dopants to diffuse into the source/drain regions without causing implantation damage. This substitution of the doping mechanism eliminates the harmful effects of ion bombardment while achieving the desired doping profile.
Solution Approach 2:
The patent changes the key parameter of junction depth by controlling diffusion conditions (temperature, time, dopant concentration) rather than relying on ion implantation energy. By adjusting diffusion parameters, shallow junctions can be formed with precise depth control, avoiding the deep junctions that occur with conventional implantation methods. The diffusion process allows for better parameter control to achieve the desired shallow junction profile.
2Reliability
If high thermal budget annealing is applied to cure implantation damage, then damage can be reduced, but transient-enhanced diffusion occurs worsening junction depth control
Solution Approach 1:
The patent performs preliminary doping through chemical diffusion before any annealing steps, so that dopants are already in the substrate without implantation damage requiring cure. The diffusion process inherently avoids creating the damage that would require high-temperature annealing to repair. By performing the doping action in advance through a damage-free method, the need for subsequent damage-curing anneals is eliminated, preventing transient-enhanced diffusion.
3Productivity
If geometry size is scaled down to increase functional density, then production efficiency improves, but power dissipation increases
Solution Approach 1:
The patent applies local quality by creating highly doped regions specifically in the source/drain areas adjacent to the channel, while maintaining lower doping in other regions. The chemical diffusion process enables precise spatial control of dopant concentration, creating localized high-doping regions that reduce source/drain resistance and power dissipation without affecting other parts of the device. This localized doping approach allows scaling to higher functional density while controlling power loss in critical regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces source/drain resistances and junction depth, minimizing transient-enhanced diffusion and short-channel effects, while maintaining high N-type dopant concentration, thus enhancing the performance and efficiency of N-type transistors.
Implementation Method 1
a rapid thermal annealing process at a lower temperature, which drives N-type dopants into the source/drain regions
Implementation Method 2
the use of a diffusion barrier to prevent over-diffusion of dopants
Data Source
AI summary
A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.