Near-Data Processing Memory Device With Engine Scheduler
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Solution Overview
Problem
Conventional computer systems face limitations in improving performance due to restricted bandwidth for communication between memory devices and processors, hindering efficient near-data processing (NDP) operations.
Innovation Solution
A memory device configuration that includes memory cell regions, NDP engines, a command buffer, and an engine scheduler, allowing for efficient NDP operations by directly accessing memory vaults within the device and utilizing an internal memory network to schedule and perform read/write requests, thereby improving data processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in a memory device and processed by a separate processor, then data storage capacity is improved, but communication bandwidth between memory device and processor becomes a performance bottleneck
Solution Approach 1:
The patent merges the processor functionality directly into the memory device by integrating multiple NDP engines within the memory device structure. This allows data processing to occur at the location where data is stored, eliminating the need for frequent data transfer between separate memory and processor components, thereby resolving the bandwidth bottleneck while maintaining storage capacity.
Solution Approach 2:
The patent introduces a new dimensional aspect to memory devices by adding multiple independent NDP engines that operate in parallel within the memory device. This transforms the traditional single-function memory device into a multi-functional processing node, enabling simultaneous data storage and processing operations without increasing external communication bandwidth requirements.
2Productivity
If multiple NDP engines are integrated within a memory device, then near-data processing performance is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory device into multiple independent functional units, each containing an NDP engine associated with specific memory vaults. This segmentation allows each engine to operate independently on its designated memory region, simplifying the control logic for each unit while achieving high overall processing performance through parallel operation of multiple segments.
Solution Approach 2:
The patent designs each NDP engine to be a universal processing unit capable of performing various near-data processing operations on its associated memory vaults. This multi-functionality reduces device complexity by using identical standardized engine designs throughout the system, rather than requiring specialized circuits for each processing task.
3Speed
If NDP engines directly access memory vaults without passing through internal memory network, then read speed is improved, but device complexity increases due to direct coupling requirements
Solution Approach 1:
The patent segments the memory device into distinct regions where specific NDP engines are directly coupled to specific memory vaults. This segmentation creates dedicated access paths that eliminate the need for these engines to traverse the general-purpose internal memory network, thereby improving read speed for their designated memory regions while isolating the direct coupling complexity to specific segments rather than the entire device.
Data Source
AI summary
A memory device includes a memory cell region including a plurality of memory cells; a memory cell controller configured to control read and write operation for the memory cell region; one or more NDP engines configured to perform a near data processing (NDP) operation for the memory cell region; a command buffer configured to store an NDP command transmitted from a host; and an engine scheduler configured to schedule the NDP operation for the one or more NDP engines according to the NDP command.