NDR Device Using Complementary MOSFETs for High PVCR

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Solution Overview

Problem

Existing negative differential resistance (NDR) devices face challenges in process control complexity, low peak-to-valley current ratio (PVCR), and area efficiency, hindering their application in RF circuits and memory designs, particularly in Si technology.

Innovation Solution

A novel NDR structure comprising a voltage blocker and current blocker MOSFETs with complementary polarity, connected in a source-coupled configuration, providing negative differential resistance and enabling CMOS compatibility and area efficiency, with an access transistor for memory functionality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional NDR device structures are used, then negative differential resistance is achieved, but the peak-to-valley current ratio (PVCR) is too small for memory applications

Engineering Contradiction:

ImprovePVCRVSAvoidswitching speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The NDR device is segmented into two distinct transistor components with opposite polarities (first transistor and second transistor with opposite polarity). This segmentation allows independent optimization of each transistor's characteristics to achieve both high PVCR and fast switching speed, resolving the contradiction between reliability and productivity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention changes the polarity parameter of the transistors by using complementary MOSFET structures (NMOS and PMOS). This parameter change enables the device to achieve high PVCR through the complementary action of the two transistors while maintaining fast switching characteristics inherent to MOSFET technology.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If NDR devices are designed for high PVCR, then memory application suitability improves, but the manufacturing process becomes complicated and less compatible with Si technology

Engineering Contradiction:

ImprovePVCRVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The invention uses standard CMOS-compatible MOSFET structures that can be manufactured using existing silicon technology processes. The complementary transistor design is universal and can be integrated into standard CMOS fabrication lines, achieving high PVCR without complicating the manufacturing process.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Speed

If NDR devices are designed for fast switching speed, then RF circuit application improves, but the PVCR becomes too small for memory applications

Engineering Contradiction:

Improveswitching speedVSAvoidPVCR

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The invention creates a composite device structure combining two transistors with opposite polarities (complementary MOSFETs). This composite structure leverages the fast switching characteristics of MOSFETs while achieving high PVCR through the interaction between the complementary transistors, simultaneously satisfying both speed and reliability requirements.

Inventive Principle:

Principle #40Composite materials

4Speed

If SRAM is used for memory applications, then fast switching speed is achieved, but the area occupied is considerable

Engineering Contradiction:

Improveswitching speedVSAvoidmemory cell area

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The invention merges the advantages of DRAM (small area) and SRAM (fast switching) into a single NDR-based memory cell structure. By combining the complementary transistors in a compact configuration, the device achieves fast switching comparable to SRAM while occupying significantly less area, effectively merging the benefits of both memory types.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed NDR device achieves high PVCR, fast switching speed, and area efficiency, simplifying the manufacturing process while maintaining CMOS compatibility, enabling efficient memory operations and reduced power consumption.

Implementation Method 1

A negative differential resistance (NDR) device has the characteristic of negative differential resistance on its current-versus-voltage curve. Namely, the current is decreasing while the voltage is increasing.

Methodology Applied

Scientific EffectNegative differential resistance:

Implementation Method 2

the value of current of those devices might depend on some sensitive factors (tunneling current, trapping effect, etc., for examples)

Methodology Applied

Scientific EffectTunneling current:

Data Source

PatentUS8283730B2Negative differential resistance device with high PVCR and fast switching speed and memory using the same

Publication Date: 2012.10.09 CHEN SHU LU

AI summary

A negative differential resistance (NDR) device is designed and a possible compact device implementation is presented. The NDR device includes a voltage blocker and a current blocker and exhibits high peak-to-valley current ratio (PVCR) as well as high switching speed. The corresponding process and design are completely compatible with contemporary Si CMOS technology and area efficient. A single-NDR element SRAM cell prototype with a compact size and high speed is also proposed as its application suitable for embedded memory.