NDR Virtual Ground Isolation for Sleep-Mode Leakage Reduction
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Solution Overview
Problem
Sub-threshold leakage current significantly contributes to power consumption in semiconductor chips, especially during sleep mode, and existing methods to reduce it require redundant storage elements that increase silicon resource usage and power consumption.
Innovation Solution
A method that uses an NDR isolation device and a virtual ground control device to isolate and raise the voltage at a virtual ground node, eliminating or reducing sub-threshold leakage current while allowing state information retention without redundant storage elements by coupling the logic block to a positive power supply and a virtual ground node, and controlling the voltage to minimize leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is shrunk to increase circuit density, then productivity and cost are improved, but sub-threshold leakage current increases leading to higher power consumption
Solution Approach 1:
The power supply system is segmented into multiple virtual power nodes (VDD1, VDD2, VDD3) with different voltage levels. Each node can be independently controlled to provide appropriate voltage to different circuit blocks, allowing leakage reduction in low-activity blocks while maintaining full performance in active blocks.
Solution Approach 2:
The patent dynamically changes the voltage parameter at different power nodes based on circuit activity. By adjusting voltage levels at virtual power nodes, the system optimizes power consumption while maintaining functionality, directly addressing the leakage issue caused by device scaling.
2Use of energy by moving object
If sleep mode is implemented to reduce sub-threshold leakage current, then power consumption is reduced, but state information is lost in storage elements
Solution Approach 1:
Storage elements are segmented into two groups: those connected to virtual power nodes that can enter sleep mode for leakage reduction, and those connected to the real power node that remain active to retain state information. This segmentation allows simultaneous power savings and data retention.
Solution Approach 2:
The patent introduces virtual power nodes as intermediary elements between the real power supply and circuit blocks. These virtual nodes act as mediators that can be independently controlled to enable sleep mode in certain blocks while maintaining power supply to storage elements that need to retain state.
3Loss of information
If redundant storage elements are used to maintain state information during sleep mode, then information retention is improved, but silicon resource usage and power consumption increase
Solution Approach 1:
The power distribution network is segmented into multiple virtual nodes, allowing selective power supply to different storage elements. This eliminates the need for redundant storage by enabling some storage elements to remain powered while others enter sleep mode.
Solution Approach 2:
The virtual power nodes serve multiple functions: they provide power to active circuits, enable sleep mode for leakage reduction, and selectively maintain power to storage elements for state retention. This multi-functionality replaces the need for dedicated redundant storage structures.
4Use of energy by moving object
If high threshold transistors are used to reduce leakage current, then power consumption is reduced, but voltage drop increases affecting logic block operation
Solution Approach 1:
The power supply is segmented into multiple virtual nodes with different voltage levels. By providing appropriate voltage levels at each node, the system compensates for the voltage drop caused by high threshold transistors while maintaining overall power efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively minimizes sub-threshold leakage current during sleep mode while maintaining state information, reducing power consumption and silicon resource usage by isolating the logic block and adjusting the virtual ground node voltage, eliminating the need for redundant storage elements.
Implementation Method 1
An NDR isolation device is coupled between the virtual ground node and ground. A virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes the NDR isolation device to isolate the virtual ground node from ground.
Data Source
AI summary
A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.