Near-Data Processing in Solid State Drives
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Solution Overview
Problem
In existing SSDs, near-data processing is performed at low speed due to the indirect control of flash memories by host devices, making it difficult to optimize data arrangement and requiring temporary storage in DRAM, which increases latency and reduces throughput.
Innovation Solution
A software-defined SSD configuration that includes a host interface circuit, an arithmetic circuit, and a memory interface circuit, allowing direct control of flash memories and performing arithmetic operations on data without the need for DRAM, thereby enabling high-speed arithmetic processing comparable to data reading speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If near-data processing is implemented in conventional SSDs with indirect flash memory control, then arithmetic operations can be performed on stored data, but processing speed is reduced due to latency and DRAM temporary storage requirements
Solution Approach 1:
The patent extracts the arithmetic circuit from the conventional SSD controller and integrates it directly into the flash memory chip structure. This extraction eliminates the indirect control path through the host device and removes the requirement for DRAM temporary storage, allowing arithmetic operations to be performed directly on data within the flash memory array at high speed.
Solution Approach 2:
The patent merges the arithmetic circuit with the flash memory array to create an integrated near-data processing system. The arithmetic circuit is positioned adjacent to the flash memory cells, enabling direct data processing without external intervention. This merging eliminates the latency associated with indirect control and DRAM buffering, achieving arithmetic processing speeds comparable to data reading speeds.
2Adaptability or versatility
If indirect control of flash memories by host devices is used, then system compatibility is maintained, but data arrangement optimization is difficult and latency increases
Solution Approach 1:
The patent introduces a controller that acts as an intermediary between the host device and the integrated flash memory-arithmetic circuit system. The controller maintains system compatibility by accepting standard host commands while enabling optimized direct control paths for arithmetic operations. This intermediary structure allows the flash memory array to be directly controlled for data arrangement optimization without sacrificing external system compatibility.
3Adaptability or versatility
If DRAM temporary storage is used for near-data processing, then arithmetic operations can be performed, but throughput is reduced and latency is increased
Solution Approach 1:
The patent extracts the arithmetic processing function from the DRAM-based temporary storage architecture and implements it directly within the flash memory array. This eliminates the need for data to be transferred to and from DRAM, removing the throughput bottleneck and latency overhead associated with temporary storage operations.
Solution Approach 2:
The patent enables the flash memory array to perform arithmetic operations on its own stored data without requiring external DRAM resources. The integrated arithmetic circuit processes data directly within the flash memory structure, making the system self-sufficient and eliminating dependency on separate temporary storage components that limit throughput.
Data Source
AI summary
A memory stores data, a memory interface circuit reads the data from the memory, and an arithmetic circuit performs a prescribed arithmetic operation on the data. A host interface circuit outputs an arithmetic request to the arithmetic circuit, and also outputs a reading instruction to the memory via the memory interface circuit, upon receipt of an arithmetic instruction from a host device. The host interface circuit receives, from the arithmetic circuit, an arithmetic result of the prescribed arithmetic operation performed on the data read from the memory via the memory interface circuit, and outputs the arithmetic result to the host device.