Near-Memory Binary Neural Network Circuit With Two-Valued Arithmetic
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Solution Overview
Problem
Existing near-memory binary neural network architectures face challenges in terms of performance, power consumption, and surface area, particularly due to the need for computationally expensive operators and gating mechanisms in hardware porting.
Innovation Solution
A circuit design comprising memory elements and computing circuits that utilize two-valued arithmetic functions to generate output vectors, incorporating logic gates, multiplexers, and a scheduler to optimize operations such as scalar products and masking, allowing for efficient binary neural network computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If computationally expensive operators and gating mechanisms are used in hardware porting, then the neural network can perform complex operations, but power consumption increases
Solution Approach 1:
The patent changes the parameter space from real numbers to binary values {0,1}, transforming complex floating-point operations into simple binary operations. This parameter transformation enables the use of XOR gates and binary multipliers instead of complex floating-point units, dramatically reducing power consumption while maintaining computational capability through binary neural network operations
Solution Approach 2:
The patent replaces traditional mechanical/computational systems with binary-based systems. Complex operators are substituted with binary-friendly operations using XOR gates for addition and simple binary multipliers, eliminating the need for power-intensive floating-point arithmetic units while preserving essential neural network functionality
2Adaptability or versatility
If computationally expensive operators are used in hardware porting, then the neural network can perform complex operations, but the surface area increases
Solution Approach 1:
By transforming parameters to binary space, the patent enables the use of compact binary operators. Binary multipliers and XOR-based adders occupy significantly less silicon area compared to floating-point units, allowing complex neural network operations to be performed with reduced hardware footprint
Solution Approach 2:
The patent creates a universal binary operator set that can perform multiple functions (addition via XOR, multiplication via AND, activation functions via binary operations) using the same hardware components, increasing adaptability while reducing the need for specialized expensive operators that would increase surface area
3Adaptability or versatility
If traditional arithmetic operations are used in near-memory architecture, then comprehensive calculations can be performed, but the activity rate of operators decreases
Solution Approach 1:
The patent transforms arithmetic operations to binary parameter space, enabling operators to process data directly in binary form without conversion overhead. This allows operators to remain active throughout the computation pipeline, performing binary operations at each stage from memory read to output generation, maximizing operator activity rate while maintaining comprehensive calculation capability
Solution Approach 2:
The patent applies binarization transformations preliminarily to convert real-valued weights and activations to binary form before computation. This preliminary action enables subsequent operators to work exclusively in binary space, increasing their activity rate by eliminating the need for floating-point arithmetic and associated conversion operations
Data Source
AI summary
The present disclosure relates to a circuit comprising a first memory element configured to store a first data value; a second memory element configured to store a weight matrix in association with a layer of a binary neural network; and a computing circuit configured to: a) receive the first data value and the k-th row of the weight matrix; b) receive a first control signal, indicating the nature of each of the first and second read functions, each associated with two-valued arithmetic; c) generate a first vector by applying the first read function to the k-th row of the weight matrix and a second vector by applying the second read function to the data; and d) generate a k-th component of a first output vector based on the first and second vectors.