Near-Memory Processing Command Arbitration for Interference Prevention
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Solution Overview
Problem
Existing Processing In Memory (PIM) techniques face challenges in synchronizing PIM commands from multiple processor threads to prevent data overwrite in near-memory processing elements, leading to errors.
Innovation Solution
A memory controller manages PIM commands by issuing them on a processor thread-by-processor thread basis, using thread identification information and last command information to defer PIM commands from other threads until the previous thread's commands are completed, thus preventing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor threads issue PIM commands to the same PIM-enabled memory simultaneously, then throughput and resource utilization are improved, but data overwrite errors occur in near-memory processing elements
Solution Approach 1:
The patent introduces a memory controller as an intermediary between processor threads and PIM-enabled memory. The memory controller includes a command queue and arbitration logic that receives PIM commands from multiple threads, queues them, and issues them in an order that prevents data overwrite errors in near-memory processing elements, thus maintaining both high throughput and data correctness
Solution Approach 2:
The patent implements preliminary ordering and queuing of PIM commands in the memory controller before they are issued to the PIM-enabled memory. By pre-organizing commands in the command queue based on thread ownership and memory element associations, the system prevents potential data overwrite errors before they can occur, ensuring data correctness while maintaining throughput
2Reliability
If processor threads synchronize to prevent data overwrite in near-memory processing elements, then data correctness is maintained, but system complexity increases due to address-to-memory element mapping requirements
Solution Approach 1:
The memory controller acts as an intermediary that handles all synchronization logic internally through its command queue and arbitration mechanisms. Processor threads simply issue commands without needing to implement complex synchronization protocols or be aware of address-to-memory element mappings, thus maintaining data correctness while keeping the threads simple
Solution Approach 2:
The memory controller's arbitration logic automatically manages command ordering and thread coordination without requiring external synchronization from processor threads. The system self-regulates to prevent data overwrite errors through internal queue management and command issuance control, eliminating the need for complex thread-level synchronization
3Reliability
If near-memory processing registers are statically assigned to processor threads, then data overwrite errors are prevented, but register utilization efficiency decreases during times when not all threads are active
Solution Approach 1:
The patent implements dynamic register allocation where near-memory processing registers are not permanently bound to specific threads but are allocated based on which thread currently has pending commands. The memory controller's arbitration logic dynamically assigns registers to active threads, allowing the same register to be reused by different threads at different times, thus preventing data overwrite errors while maximizing register utilization efficiency
Solution Approach 2:
Near-memory processing registers are designed to be universal resources that can serve multiple processor threads rather than being dedicated to single threads. The memory controller manages this shared access by queuing and ordering commands, allowing any thread to use any register when needed, thus improving resource utilization while maintaining data correctness through controlled access
Data Source
AI summary
An approach is provided for managing near-memory processing commands (“PIM commands”) from multiple processor threads in a manner to prevent interference and maintain correctness at near-memory processing elements. A memory controller uses thread identification information and last command information to issue a PIM command sequence from a first processor thread, directed to a PIM-enabled memory element, while deferring the issuance of PIM command sequences from other processor threads, directed to the same PIM-enabled memory element. After the last PIM command in the PIM command sequence for the first processor thread has been issued, a PIM command sequence for another processor thread is issued, and so on. The approach allows multiple processor threads to concurrently issue fine grained PIM commands to the same PIM-enabled memory element without having to be aware of address-to-memory element mapping, and without having to coordinate with other threads.