Near-Memory Controller Mode Switching for Memory Efficiency
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Solution Overview
Problem
The increasing computational demands of electronic devices pose challenges in efficiently allocating high-capacity and high-speed memory resources, particularly due to limited resources and the need for optimized memory channel control to enhance processing speed, reduce power consumption, and support various memory layers.
Innovation Solution
The implementation of a system-on-chip (SoC) with near-memory and far-memory controllers, allowing memory channels to operate in multiple modes, with the near-memory device supporting both cache and main memory operations based on mode settings, and the far-memory device providing additional storage capacity with independent control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a high-capacity memory device is allocated for all calculations/computations, then the storage capacity is improved, but the resource allocation efficiency deteriorates due to limited electronic device resources
Solution Approach 1:
The memory system is segmented into multiple independent memory channels (first memory channel, second memory channel) that can be independently controlled and configured. Each channel can operate in different modes (cache mode, main memory mode) based on specific computational needs, allowing efficient resource allocation without sacrificing overall capacity.
Solution Approach 2:
The memory channels are designed to dynamically change their operation modes based on computational requirements. The first memory channel can switch between cache mode and main memory mode through mode register write commands, enabling the system to adapt resource allocation to varying computational demands in real-time.
2Device complexity
If memory channels are controlled with fixed modes, then the device complexity is reduced, but the adaptability to different calculation types deteriorates
Solution Approach 1:
The memory channels utilize mode register write (MRW) commands to change operational parameters such as cache line size, timing parameters, and memory mode configuration. This allows the same hardware to support multiple operation modes (cache mode, main memory mode) by simply changing register values without modifying the physical structure or control logic complexity.
3Device complexity
If a single memory controller manages all memory channels, then the device complexity is reduced, but the processing speed deteriorates due to resource bottlenecks
Solution Approach 1:
The memory controller is segmented into multiple independent controllers (first memory controller, second memory controller) that can independently manage different memory channels. This parallel control structure eliminates bottlenecks by allowing simultaneous operation of multiple memory channels without interference, thereby increasing overall data processing speed while maintaining relatively simple individual controller designs.
Data Source
AI summary
An electronic device includes: a system-on-chip (SoC) including a processor, a near-memory controller controlled by the processor, and a far-memory controller controlled by the processor; a near-memory device including a first memory channel configured to communicate with the near-memory controller and operate in a first mode of a plurality of modes, and a second memory channel configured to communicate with the near-memory controller and operate in a second mode different from the first mode from among the plurality of modes; and a far-memory device configured to communicate with the far-memory controller. The first memory channel is further configured to, based on a command from the near-memory controller, change an operation mode from the first mode to the second mode.