Near-Memory FHE Polynomial Processing Across Enclave Tiles
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Solution Overview
Problem
Fully homomorphic encryption (FHE) operations are time-consuming and inefficient due to the need for large off-chip data transfer, as conventional hardware like CPUs and GPUs struggle with processing long and wide polynomials, and existing ASICs with large on-chip memory are insufficient for storing large keys.
Innovation Solution
A near memory processing device with a hierarchy of enclaves and interconnected tiles, where coefficients of polynomials are decomposed into levels, allowing for parallel processing of operations across enclaves and tiles, utilizing DRAM internal bandwidth for efficient computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional hardware (CPUs/GPUs) is used for FHE operations, then general-purpose computing is maintained, but processing speed is orders of magnitude slower due to small on-chip memory and frequent off-chip data transfer
Solution Approach 1:
The patent segments the FHE processing system into specialized components: polynomial processing units that handle specific polynomial operations, coefficient storage units dedicated to storing polynomial coefficients, and key storage units for cryptographic keys. This segmentation allows each component to be optimized for its specific function, dramatically improving FHE operation speed while maintaining general-purpose adaptability through configurable processing units.
Solution Approach 2:
The patent introduces on-chip memory structures as intermediaries between the CPU and off-chip memory. These intermediaries (coefficient storage units and key storage units) cache frequently accessed data, reducing the frequency of slow off-chip data transfers and accelerating FHE operations while the system remains programmable for general-purpose use.
2Productivity
If ASIC with large on-chip memory is used, then FHE operation speed is improved by reducing off-chip data transfer, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent designs polynomial processing units with configurable parameters that allow the same hardware structure to handle different polynomial operations (addition, multiplication, NTT, INTT) and different polynomial sizes. This multi-functionality reduces device complexity compared to dedicated ASICs for each operation, while still providing on-chip storage and fast processing for improved FHE operation speed.
Solution Approach 2:
The patent employs parameterizable polynomial processing units where key parameters (polynomial degree, coefficient bit-width, operation type) can be configured through software rather than hardwired. This allows the same hardware architecture to adapt to different FHE schemes and operation requirements, reducing manufacturing complexity while maintaining high performance for various cryptographic applications.
3Measurement precision
If polynomial coefficients are processed as complete large datasets, then computational accuracy is maintained, but data transfer volume between memory and processor increases
Solution Approach 1:
The patent segments large polynomial coefficient datasets into smaller blocks that fit within on-chip coefficient storage units. Each block can be processed independently or in parallel, maintaining full computational accuracy through proper block-wise arithmetic operations while dramatically reducing the volume of data that must be transferred between memory and processor during FHE operations.
Solution Approach 2:
The patent implements preliminary loading of polynomial coefficients and cryptographic keys into on-chip storage units before processing begins. This preliminary action ensures that all necessary data is available in fast on-chip memory, eliminating the need for repeated data transfers during the actual FHE computations and reducing overall data transfer volume while preserving computational accuracy.
Data Source
AI summary
Provided are a device, system, and computer program product for a near memory processing device to process coefficient elements resulting from decomposition of polynomials. A near memory processing device includes a plurality of enclaves and a plurality of interconnected tiles on each enclave. Coefficients of a polynomial are decomposed into a number of levels of the coefficient elements. Each level of coefficient elements comprises a limb. A device control receives hierarchical commands, from an application, that map operations to perform on limbs of coefficient elements to the enclaves and that map operations for the enclaves to the tiles in the enclaves. The device controller distributes operations for the tiles in the hierarchical commands to perform on the coefficient elements to the enclaves to distribute operations to perform on the coefficient elements to the tiles.